一种基于AND-LUT的混合FPGA结构

提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.     

适用于数据通路的可编程逻辑器件FDP100K

设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;连线资源结构采用新颖的层次式布线结构,提供高度灵活的布线能力.芯片采用SMIC 0.35 μm CMOS工艺,包含1024个可编程逻辑单元和128个可编程IO单元.芯片配合自主开发的软件系统FDE(FPGA Development Environment)进行测试,结果表明:FDP100K芯片的可编程逻辑单元功能正常;芯片的各种连线资源功能正常;可以准确地实现数据通路型电路和其他类型的电路的功能.     

具有高资源利用率特征的改进型查找表电路结构与优化方法

该文着重研究了FPGA芯片中核心模块基本可编程逻辑单元(BLE)的电路结构与优化设计方法,针对传统4输入查找表(LUT)进行逻辑操作和算术运算时资源利用率低的问题,提出一种融合多路选择器的改进型LUT结构,该结构具有更高面积利用率;同时提出一种对映射后网表进行统计的评估优化方法,可以对综合映射后网表进行重新组合,通过预装箱产生优化后网表;最后,对所提结构进行了实验评估和验证。结果表明:与Intel公司Stratix系列FPGA相比,采用该文所提优化结构,在MCNC电路集和VTR电路集下,资源利用率平均分别提高了10.428% 和 10.433%,有效提升了FPGA的逻辑效能。     

一种FPGA新型逻辑单元结构的设计

提出了一种FPGA可编程逻辑单元的新结构,该结构具有较多的输入端数和输出端数,并加入了专用的快速进位逻辑、专用级联链等功能,使得这种结构可用来实现任意4输入的逻辑函数和某些高达11个变量的输入函数;这种结构还可同时实现两个任意3输入的逻辑函数或最多5输入的某些函数,而且也能实现快速的进位计算和高扇入的逻辑运算.与目前一些商业FPGA的逻辑结构进行比较表明,本文提出的单元结构不仅具有较高的资源利用率,而且在性能和函数实现能力上都有较大的优势.     

非制冷红外焦平面阵列信号处理系统设计

介绍了320×240非制冷红外焦平面阵列(UFPA)的信号处理系统;采用复杂可编程逻辑器件(FPGA)产生红外焦平面阵列的驱动时序,应用数字信号处理(DSP)技术实现红外焦平面阵列的非均匀校正.实验及仿真结果表明:FPGA可产生焦平面阵列所需时序,DSP对焦平面阵列的非均匀校正效果较好.     

基于FPGA的电机控制器的设计

文中给出了一种基于现场可编程阵列(FPGA)器件的电机控制器设计方案,利用可编程逻辑器件的特点将电机控制所需的逻辑控制单元电路及外围接口电路等集成在一片FPGA中,提高了整个控制器的稳定性和可靠性;同时利用FPGA灵活的编程特点,可实现较复杂的电机控制算法,进而提高了控制性能;另外FPGA具有现场可重构的特性,保证了所设计的电机控制模块具有良好的可维护性,也大大方便了系统的设计和调试。     

满足应用和发展的需求,XILINX推出多项FPGA最新产品

现场可编程门阵列(FPGA)由掩模可编程门阵列(MPGA)和可编程逻辑器件(PLD)两者演变而来并将它们的特性结合在一起,因此FPGA既有门阵列的高逻辑密度和通用性,又有可编程逻辑器件的用户可编程特性.它通常由布线资源围绕的可编程逻辑单元构成阵列,又由可编程I/O单元围绕阵列构成整个芯片,排成阵列的逻辑单元由布线通道中的可编程内连线连结起来实现一定的逻辑功能.对于ASIC设计来说,采用FPGA在实现小型化、集成化和高可靠性的同时,减少了风险,降低了成本,缩短了周期.这些特点使FPGA近年来发展迅速.Xilinx公司为适应各种应用的需要,在1995年推出多个新产品系列,如有双口RAM的XC4000E,大容量低成本的XC5200系列,反熔丝型门海结构的XC8100系列和可再配置协处理器的XC6200系列等,以及XACT6.0开发系统,由此也可看出FPGA的发展势头.本文以XC8100系列为主对其新产品作一介绍.     

FPGA在恶劣电磁环境下的抗干扰设计

在恶劣电磁环境下,对现场可编程逻辑阵列(FPGA)工作稳定性影响较大的是外界杂波脉冲和毛刺信号.从FPGA芯片内部设计和外部设计两方面介绍了提高FPGA芯片工作稳定性的一些措施.     

基于QCA可编程逻辑阵列单元的元胞缺陷研究

介绍了一种量子元胞自动机(QCA)可编程逻辑阵列结构,该结构可用于实现量子元胞自动机大规模可编程逻辑电路,采用QCADesigner仿真软件研究了元胞缺失、移位缺陷和未对准缺陷对可编程逻辑阵列单元逻辑功能的影响。得出了特定结构下,每个元胞移位缺陷和未对准缺陷的最大错位距离,以及导线模式中存在特定位置的8个可缺失元胞。这为缺陷单元的应用提供了一个具体的参数标准,提高了PLA阵列的单元利用率。     

一种采用四/五输入可配置查找表结构和优化进位链的新型FPGA

本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.     

Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs

Mapping digital circuits onto field-programmable gate arrays (FPGAs) usually consists of two steps. First, circuits are mapped into look-up tables (LUTs). Then, LUTs are mapped onto physical resources. The configuration of LUTs is usually determined during the first step and remains unchanged throughout the second. In this paper, we demonstrate that by reconfiguring LUTs during the second step, one can increase the flexibility of FPGA routing resources. This increase in flexibility can then be used to reduce the implementation area of FPGAs. In particular, it is shown that, for a logic cluster with $ I$ inputs and $ N$ $ k$-input LUTs, a set of $Ntimes kquad (I+N-k+1):1$ multiplexers can be used to connect logic cluster inputs to LUT inputs while maintaining logic equivalency among the logic cluster I/Os. The multiplexers (called a local routing network) are shown to be the minimum required to maintain logic equivalency. Comparing to the previous design, which employs a fully connected local routing network, the proposed design can reduce logic cluster area by 3%–25% and can reduce a significant amount of fanouts for logic cluster inputs.      

The effect of LUT and cluster size on deep-submicron FPGA performance and density

In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs (Betz et al. 1997) we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. We use a fully timing-driven experimental flow (Betz et al. 1997), (Marquardt, 1999) in which a set of benchmark circuits are synthesized into different cluster-based (Betz and Rose, 1997, 1998) and (Marquardt, 1999) logic block architectures, which contain groups of LUTs and flip-flops. Across all architectures with LUT sizes in the range of 2 to 7 inputs, and cluster size from 1 to 10 LUTs, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that clustering small LUTs (sizes 2 and 3) produces better area results than what was presented in the past. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 3-10 provides the best area-delay product for an FPGA.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This paper describes such an FPGA routing architecture, called the multibit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, compared to conventional FPGA routing architectures, the multibit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall FPGA area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections.     

Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

This article introduces a novel lookup table (LUT) and its usage in the configurable logic block (CLB) architectures for SRAM-based field-programmable gate array (FPGA) architectures. The proposed CLB allows sharing of SRAM tables of LUTs among NPN-equivalent functions to reduce the size of memories used for storing the functions and also reduces the number of configuration bits required. We measured many different characteristics of FPGAs using our new CLB architecture, including area, delay, routing, and power requirements. We experimentally found that for many different FPGA architectures, CLBs can share one-fourth of their SRAM tables between two basic logic elements (BLEs), which reduced both power consumption and area without negatively affecting routing or wirelength, and there was only a negligible increase in critical path delay of 0.27%. Specifically, we find that FPGAs consisting of CLBs with 16 BLEs and 34 inputs can be implemented with eight normal SRAMs and four SRAMs shared between two BLEs, for an overall reduction of four out of sixteen SRAM tables per CLB. With this new CLB architecture, we measured an approximate reduction in overall power consumption of 2% and an estimated reduction in area of 3%     

CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs

Field programmable gate arrays usage has been growing steadily for years now. Their popularity stems from the fact that they can be reprogrammed to implement any function, with any amount of parallelism. Unfortunately, exactly due to their flexibility, FPGAs require a huge amount of resources, in the form of LUTs and routing switches, and these can take up to 90% of the chip area. In this paper we present the development of a low-power full CMOS multiple-valued logic to build a LUT for FPGAs. Several circuits are mapped to quaternary LUTs and compared to their binary counterpart. Results show great improvements in terms of area and power consumption. Moreover, we show the positive impact of the proposed architecture in the global reduction of routing switches and wiring, and hence in the total FPGA area.