共查询到20条相似文献,搜索用时 140 毫秒
1.
2.
针对导航系统所存在的软故障及其特性,并结合小波信号分析的特点,提出了基于小波分析的组合导航系统故障检测的方法,采用该方法对含有软故障的组合导航系统信息的量测信号进行处理与分析,从而达到故障检测的目的,将此方法应用于捷联惯性导航系统/全球定位系统(SINS/GPS)组合导航系统的故障检测。对仿真结果的分析表明,该方法可以检测出组合导航系统的所存在的软故障,并且更加简便灵活,效果明显。 相似文献
3.
4.
故障检测和隔离对提高无人机的导航精度和可靠性有重要意义.针对残差卡方算法对小值软故障灵敏度差,改进序贯概率比(SPRT)算法无法判断故障结束时间的缺陷,提出了一种联合故障检测算法.该算法依靠残差卡方算法判断故障结束时间,从而及时对改进SPRT算法检测值进行修正,使改进SPRT算法能继续检测非第一次故障.改进SPRT算法对故障的灵敏度高,且残差卡方算法能准确判别故障结束时间.仿真结果表明,该综合算法对小值软故障、大值阶跃故障都有很好的检测效果,有效提高了系统的故障检测能力及灵敏度,增强了组合导航系统的可靠性. 相似文献
5.
文中主要针对综合导航系统对于缓变故障检测困难,以及故障难以定位等问题,提出一种基于状态χ^2。检验和ARTMAP神经网络技术的故障检测与诊断系统。用基于BP神经网络的状态χ^2检验法检测出故障数据后,以故障时刻的SCST值作为两个ARTMAP网络的输入模式,判断故障源、故障幅值和故障发生时间。并以SINS/GPS综合导航系统实际跑车数据为基础进行缓变故障仿真,验证该方法的有效性和检测精度。 相似文献
6.
捷联惯性导航系统(SINS)/视觉组合导航系统的融合算法主要是卡尔曼滤波,卡尔曼滤波实现最优估计的前提是系统的模型必须准确已知。对于SINS/视觉组合导航系统,获取量测信息需经图像处理、特征点提取和匹配等过程,使量测噪声统计模型不完全可知,这会导致卡尔曼滤波器的估计精度下降。因此,该文提出一种改进的自适应两级卡尔曼滤波,根据求解遗传因子的不同方法对传统自适应两级卡尔曼滤波进行改进。改进后的算法分别适用于系统噪声统计模型和量测噪声统计模型不准确可知两种情况,且二者具有统一的滤波框架。仿真结果表明,改进的自适应两级卡尔曼滤波比卡尔曼滤波精度高,有效解决了SINS/视觉组合导航系统因噪声统计模型不准确导致的精度下降问题。 相似文献
7.
不完全量测下残差检测算法的设计是光电跟踪滤波器设计的关键,算法的正确检测概率直接影响到跟踪滤波器的估计性能.为了进一步提升传统残差检测算法的正确检测概率,提出了一种基于后验置信度的残差检测算法.其主要思想是在传统残差检测算法的基础上首先增加一个检测门限,对处于两个门限之间的残差,利用模糊隶属度函数方法进行模糊化,得到残差的似然概率,进而结合跟踪系统的先验探测信息,计算出探测数据的后验置信度,并根据计算结果对跟踪系统的数据探测情况进行判定.进一步,基于后验置信度残差检测算法,在不完全量测下设计了基于无偏转换量测的光电跟踪滤波器,并给出了跟踪系统统计意义下的Cramer-Rao下界(CRLB).Monte-Carlo仿真表明:基于后验置信度残差检测的光电跟踪滤波器,与基于传统残差检测的光电跟踪滤波器相比,估计性能有了进一步提升,特别是当跟踪系统探测概率较低时,估计性能提升更加显著,并且估计误差均方差(RMSE)已逼近跟踪系统统计意义下的CRLB. 相似文献
8.
针对多模卫星系统可能存在故障卫星,而故障卫星的种类和数量往往无法灵活确定,导致系统定位失效的问题,提出了一种基于强跟踪滤波的多模卫星容错组合导航算法.设计了一种基于单元级融合方式的容错系统结构,即为每颗卫星分别设计基于强跟踪滤波技术的子滤波器和故障检测与隔离器,并提出了一种改进的残差故障检测方法,全局算法采用联邦滤波算法,最终完成了一种北斗/GPS/GLONASS容错组合导航算法的设计.实验结果表明,该算法能充分利用多个卫星系统的卫星进行定位,同时能够同步检测和隔离多个不同卫星系统的故障卫星,有效提高了系统的定位精度和可靠性. 相似文献
9.
10.
针对舰船组合导航系统的故障实时检测问题.采用复杂性系统中的近似熵测度理论,计算导航量测信号的近似熵值,利用信号的近似熵值的突变作为系统故障发生的判断标准。仿真结果表明该方法可以较好的提供监测信息。 相似文献
11.
为使AES S盒的多奇偶校验故障检测方案具备预期故障检测能力,提出了由预期故障覆盖率确定预测奇偶总数的参数计算模型.根据模型确定的预测奇偶总数,为基于冗余有限域算术的S盒定制了两种多分块多奇偶校验的故障检测方案.推导优化了各分块预测奇偶计算公式,并通过穷举搜索找到了使整个电路结构最优的多项式系数与映射矩阵.仿真结果表明两种方案的随机多故障覆盖率均约为97%,验证了参数计算模型的有效性,突发故障覆盖率分别约为61.8%、76.3%,优于已有文献中大部分故障检测方案.综合结果表明,对比于已有文献中具有相似故障检测能力的故障检测S盒电路,所设计电路的面积-延时积最小. 相似文献
12.
Altug S. Mo-Yuen Chen Trussell H.J. 《Industrial Electronics, IEEE Transactions on》1999,46(6):1069-1079
Motor fault detection and diagnosis involves processing a large amount of information of the motor system. With the combined synergy of fuzzy logic and neural networks, a better understanding of the heuristics underlying the motor fault detection/diagnosis process and successful fault detection/diagnosis schemes can be achieved. This paper presents two neural fuzzy (NN/FZ) inference systems, namely, fuzzy adaptive learning control/decision network (FALCON) and adaptive network based fuzzy inference system (ANFIS), with applications to induction motor fault detection/diagnosis problems. The general specifications of the NN/FZ systems are discussed. In addition, the fault detection/diagnosis structures are analyzed and compared with regard to their learning algorithms, initial knowledge requirements, extracted knowledge types, domain partitioning, rule structuring and modifications. Simulated experimental results are presented in terms of motor fault detection accuracy and knowledge extraction feasibility. Results suggest new and promising research areas for using NN/FZ inference systems for incipient fault detection and diagnosis in induction motors 相似文献
13.
Karri R. Kaijie Wu 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2002,10(6):864-875
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the Synopsys behavior complier (BC), to validate the schemes. 相似文献
14.
该文提出了用于MC DS-CDMA系统中的两种SDCMA(最陡下降常模算法)盲检测方法,一种是SDCMA盲均衡算法,在此基础上,提出了另一种联合均衡和多用户检测的SDCMA盲算法。同时还将这两种算法与基于子空间的MMSE(最小均方误差)盲检测算法进行比较。仿真结果表明,这两种SDCMA算法的BER(误比特率)性能均优于子空间法,而且联合均衡和多用户检测的SDCMA盲算法利用同时对均衡权值向量和多用户检测器向量进行自适应更新,能较大程度地改善系统性能,是这3种盲算法中性能最佳的一个。 相似文献
15.
《Solid-State Circuits, IEEE Journal of》1987,22(4):583-594
Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques. 相似文献
16.
To reduce excessive computing and communication loads of traditional fault detection methods, a neighbor-data analysis based node fault detection method is proposed. First, historical data is analyzed to confirm the confidence level of sensor nodes. Then a nodes reading data is compared with neighbor nodes which are of good confidence level. Decision can be made whether this node is a failure or not. Simulation shows this method has good effect on fault detection accuracy and transient fault tolerance, and never transfers communication and computing overloading to sensor nodes. 相似文献
17.
Fault detection schemes for the Advanced Encryption Standard are aimed at detecting the internal and malicious faults in its hardware implementations. In this paper, we present fault detection structures of the S-boxes and the inverse S-boxes for designing high performance architectures of the Advanced Encryption Standard. We avoid utilizing the look-up tables for implementing the S-boxes and the inverse S-boxes and their parity predictions. Instead, logic gate implementations based on composite fields are used. We modify these structures and suggest new fault detection schemes for the S-boxes and the inverse S-boxes. Using the closed formulations for the predicted parity bits, the proposed fault detection structures of the S-boxes and the inverse S-boxes are simulated and it is shown that the proposed schemes detect all single faults and almost all random multiple faults. We have also synthesized the modified S-boxes, inverse S-boxes, mixed S-box/inverse S-box structures, and the whole AES encryption using the 0.18 μ CMOS technology and have obtained the area, delay, and power consumption overheads for their fault detection schemes. Furthermore, the fault coverage and the overheads in terms of the space complexity and time delay are compared to those of the previously reported ones. 相似文献
18.
In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced. 相似文献
19.
20.
火炮故障检测系统检测范围有限和检测精度低是火炮故障诊断系统的两大缺陷,针对现有火炮检测系统检测精度低的问题,从电路设计、A/D采集电路设计以及液晶显示等方面分析了影响系统检测精度的主要因素,并提出了多种改善检测精度的方案。针对现有火炮检测系统检测范围有限的问题,提出了一个可对炮控箱、操纵台和瞄控箱、电源、开关以及电位旋钮等多位置发生的故障进行检测的火炮综合故障检测系统,并对该系统相关的硬件和软件进行了设计。测试实验表明,该系统功能完善,通用性好,改善系统检测精度的方案实用性强,对于提高我国的火炮故障检测水平具有积极的意义。 相似文献