带有ESD保护,900MHz/2.4GHz Dual-Band CMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

ESD-Protected Wideband CMOS LNAs Using Modified Resistive Feedback Techniques With Chip-on-Board Packaging

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an R–C feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNA1 and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of $-$8 and $-$9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively.      

A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.     

增益可控CMOS低噪声放大器

设计了采用SMIC0.18μm RF CMOS工艺的共源共栅NMOS结构的增益可变的差动式低噪声放大器。在考虑了ESD保护pad和封装寄生效应后,着重对低噪声放大器的输入阻抗匹配、增益以及共源共栅级联结构下的噪声系数、线性度等进行了一系列分析,并提出了优化措施。芯片测试结果表明:在1.56GHz中心频率下,-3dB带宽约为150MHz,输出最大电压增益为27dB,此时噪声系数NF约为2.33dB,IIP3约为4.0dBm,可变增益范围为7dB。在3.3V电源电压下消耗电流8.2mA。此设计方法可以应用到诸如GSM、GPS等无线接收机系统中。     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

应用于GSM/EDGE零中频接收机的CMOS射频前端

介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90...     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

2-GHz CMOS射频低噪声放大器的设计与测试

本文采用CMOS工艺,针对无线通信系统前端(Front-end)的低噪声放大器进行了分析、设计、仿真和测试.测试结果表明,该放大器工作在2.04-GHz的中心频率上,3dB带宽约为110MHz,功率增益为22dB,NF小于3.3dB.测试结果与仿真结果能够很好地吻合.     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz60 MHz low noise amplifier (LNA) designed in a 0.35 m SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of ?11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

A universal dual band LNA implementation in SiGe technology forwireless applications

A dual band low-noise amplifier (LNA) with matched inputs and outputs, implemented in Infineon Technologies' B7HF SiGe process, is presented. Both the single-ended inputs and outputs are matched to 50 Ω without external elements. For the low-band (800 MHz-1 GHz), the LNA has a measured gain of 17 dB and a noise figure below 1.2 dB at 900 MHz. The high-band (1.8-2 GHz) LNA achieves a gain of 15 dB and a noise figure below 1.5 dB at 1.9 GHz. Both LNAs consume 5 mA dc current with a power supply voltage range from 2.7-3.6 V     

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S₁₁ below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs     

A 2.4 GHz CMOS Low-IF Receiver Front-End for WLAN Applications

A CMOS low-IF receiver front-end applied for Wireless Local Area Networks (WLANs) is presented in this paper. The receiver front-end comprises a low noise amplifier (LNA), a down-converter, a single-to-fully converter, a polyphase filter, and a summator/subtractor. This low-IF architecture achieves 0.46° phase error and 0.7 dB gain mismatch in I–Q channels while the 2.4 GHz RF signal is down-converted into 100 MHz of IF band. The cascaded noise figure (NF) of LNA and polyphase network is 4.89 dB within the WLANs' requirement. The chip realized in a 0.6 m CMOS technology occupys 2.4 mm × 2.1 mm active area. From a single 3.3 V power supply, it consumes 300 mW power.     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

Millimeter‐Wave High‐Linear CMOS Low‐Noise Amplifier Using Multiple‐Gate Transistors

A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P_1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.