Thin film polycrystalline silicon nanowire biosensors

Polysilicon nanowire biosensors have been fabricated using a top-down process and were used to determine the binding constant of two inflammatory biomarkers. A very low cost nanofabrication process was developed, based on simple and mature photolithography, thin film technology, and plasma etching, enabling an easy route to mass manufacture. Antibody-functionalized nanowire sensors were used to detect the proteins interleukin-8 (IL-8) and tumor necrosis factor-alpha (TNF-α) over a wide range of concentrations, demonstrating excellent sensitivity and selectivity, exemplified by a detection sensitivity of 10 fM in the presence of a 100,000-fold excess of a nontarget protein. Nanowire titration curves gave antibody-antigen dissociation constants in good agreement with low-salt enzyme-linked immunosorbent assays (ELISAs). This fabrication process produces high-quality nanowires that are suitable for low-cost mass production, providing a realistic route to the realization of disposable nanoelectronic point-of-care (PoC) devices.     

Studying the morphology of hemispherical-grain polycrystalline silicon films

The effect of the deposition temperature on the morphology of hemispherical-grain polycrystalline silicon (HSG-Si) films obtained by low-pressure chemical vapor deposition (LPCVD) has been studied using atomic force microscopy. The dependences of the relative surface area increment, density of grains, average height and lateral size of grains, mean square roughness, and correlation length on the deposition temperature have been determined in an interval used for the LPCVD growth of HSG-Si films.     

Heterogeneous nucleation and growth of polycrystalline silicon

The heterogeneous nucleation theory of silicon on SiO₂ and Si₃N₄ substrates has been developed using classical theory. It is shown that the experimental observations can be explained on the basis of the bond energies of O-H, N-H and Si-H. A reaction model is proposed for the growth of silicon on silicon from silane, using hydrogen as a carrier gas in the temperature region 600–900°C. The growth rate of silicon is shown to be equal toP _{SiH 4} P _{H 2} when the partial pressure of hydrogen is high, and is independent of the total pressure and the partial pressure of hydrogen in the lower region.     

Novel approach to thin film polycrystalline silicon on glass

Thin (1 μm) a-Si:H films have been deposited on glass at high-deposition rate (8 nm/s) and high substrate temperature (400 °C) by the expanding thermal plasma technique (ETP). After a Solid Phase Crystallization treatment at 650 °C for 10 h, many crystal grains are found to extend over the entire thickness (1 μm) of the polycrystalline silicon (poly-Si) films. This result indicates that the scalable, high-deposition rate ETP method can contribute to increase the potential for a widespread diffusion of poly-Si based thin film solar cells on glass.     

The bending of silicon wafers by thin polycrystalline silicon film deposition and by film doping using boron diffusion

The existence of stress at the interface between a monocrystalline silicon substrate and a thin (under 1 μm) polycrystalline silicon film was demonstrated using X-ray topography. The wafer-bending direction was studied for a polycrystalline film doped by boron prediffusion and by prediffusion followed by drive-in diffusion. Wafer bending in the presence of SiO₂ thermal growth between the monocrystalline substrate and the polycrystalline film was also investigated. The causes of the wafer bending and its change during polycrystalline film doping are discussed.     

Modeling and visualization of polycrystalline thin film growth

A novel polycrystalline thin film growth simulator, FACET, has been developed. FACET is a multi-scale model with two major components: an atomic level one-dimensional kinetic lattice Monte Carlo (1D KLMC) model and a real time feature scale two-dimensional facet nucleation and growth model.

The 1D KLMC model has been developed to calculate inter-facet diffusion rates. By inputting the diffusion activation energies, the model will calculate the inter-facet atomic flux between {1 0 0}, {1 1 0}, and {1 1 1} facets of FCC materials at any temperature. The results of the 1D KLMC model have been verified by comparison with a full three-dimensional kinetic lattice Monte Carlo (3D KLMC) model.

The feature scale polycrystalline thin film nucleation and growth model is based on describing grains in terms of two-dimensional faceted surfaces and grain boundaries. The profile of the nuclei are described by crystallographically appropriate facets. The position and orientation of the nuclei can be randomly selected or preferred textures can be created. Growth rates are determined from different deposition fluxes and surface diffusion effects. Quantitative microstructural characterization tools, including roughness analysis, average grain size analysis, and orientation distribution analysis, were incorporated into the model, which allows the users to design, conduct and analyze the virtual experiments within one integrated graphical user interface. Users can also visualize the nucleation and growth process of the film and obtain the final film microstructure. The effects of thickness, temperature, and deposition flux on thin film microstructures have been studied by FACET.     

石墨衬底上多晶硅厚膜的生长及性质分析

以石墨片为衬底,利用磁控溅射技术生长多晶硅籽晶层,退火处理后用CVD制备多晶硅厚膜。XRD测试结果表明,在籽晶层上外延多晶硅厚膜具有高度的(220)取向,这说明外延层的择优取向延续了籽晶层的取向。SEM测试结果表明,石墨片上多晶硅外延层生长良好,说明石墨片作为廉价衬底之一,有望投入工业化生产,以降低太阳能电池的制作成本。     

Grain growth mechanism in heavily arsenic-doped polycrystalline silicon

The mechanism of grain growth in heavily arsenic-doped polycrystalline silicon has been investigated by developing a kinetic model. A computer simulation technique has been used to determine the grain boundary self-diffusion of the silicon atoms and hence the grain size for different arsenic concentrations, annealing times and temperatures has been estimated. The evaluated numerical values are compared with the available experimental values. Using this model the grain size distribution in arsenic-doped polysilicon for various values of arsenic concentration, annealing time and temperature has been determined. The results are discussed in detail.     

以SiCl4为源气体用PECVD技术低温快速生长多晶硅薄膜

报道了以SiCl4和H2为气源,用等离子体增强化学气相沉积技术,在小于300℃的低温下快速生长多晶硅薄膜.实验发现, 生长速率强烈依赖于放电功率、H2/SiCl4流量比和衬底温度, 而薄膜的晶化度只依赖于放电功率和H2/SiCl4流量比,与衬底温度的关系不大.通过控制和选择工艺条件,我们获得了生长速率高达0.35nm/s,晶化度高于75%的多晶硅薄膜.薄膜的暗电导率和光电导率分别达到10-4S-1·cm-1和10-3S-1·cm-1.     

The simultaneous growth of monocrystalline and polycrystalline silicon films with controlled parameters

The influence of the temperature of deposition of nucleation layers on the structure of polycrystalline silicon films which grow locally during the epitaxial growth of monocrystalline films was investigated.The structure of polycrystalline films grown in the high temperature chloride process has been found to depend on the deposition mode of the nucleation layer. For temperature changes in the range 800–860°C, the grain sizes in polycrystalline silicon increase by more than one order of magnitude.It was shown that heat treatment of films of small grain size in an atmosphere of oxygen leads to a decrease in their resistance owing to recrystallization of the grains, whereas during the annealing of films of large grain size the oxidation of intergrain boundaries is the dominant process resulting in an increase in the resistance.The possibility of using polycrystalline films fabricated under specific technological conditions for the isolation of integrated circuit elements was demonstrated.     

Investigation of chalcopyrite film growth: an evolution of thin film morphology and structure during selenization

In this work, we report a study of the evolution of Cu–In–Ga–Se system during selenization. The metallic precursors were selenized in Se vapour atmosphere at temperature range from 210 to 380 °C. Scanning electron microscopy, transmission electron microscopy, X-ray diffraction, Raman spectra were used to investigate morphological and structural properties of the films. A great amount of thin platelets appeared in the film surfaces at temperature range from 210 to 270 °C. Most platelets had hexagon or polygon structures. The average sizes of these platelets increased with the temperatures. TEM analyses indicated that these platelets had γ-CuSe phases. Beyond 310 °C, most of CuSe platelets decomposed under release of selenium and formed Cu_2?xSe. Cu_2?xSe might react with InSe for the formation of tetragonal CuInSe₂. The average grain sizes increased obviously with the increased temperatures. A possible reaction path to obtain a chalcopyrite structural film was discussed in the end. In addition, Ga was detected rich in the bottom of the film by energy dispersive spectroscopy and grazing incidence X-ray diffraction.     

Grain growth and mechanical properties in bulk polycrystalline silicon

The grain structure of bulk polycrystalline silicon has been examined as a function of annealing temperatures and times between 1000 and 1400°C and 6 to 24 hours, respectively. The initial high aspect grain structure decomposes into roughly equiaxed grains at 1000°C over the course of 24 hours. The grains proceed to grow via Oswald ripening with an activation energy for grain growth of 1.49 eV. The hardness increases slightly during annealing and the subsequent transformation to an equiaxed grain structure, from a Vickers hardness of 964 to 1160 kg/mm². The fracture toughness is 0.8 MPa(m)^1/2in the as grown structure, and increases to 1 MPa(m)^1/2in annealed samples. The hardness and fracture toughness are independent of grain size for grain diameters between 2.7 and 4 m.     

硅片载体表面形貌对蛋白质吸附的影响

采用固定金属离子亲和技术在不同表面形貌的硅基片上交联金属离子螯合物,蛋白质分子通过其末端的组氨酸标记(His-tag)与金属离子螯合,定向结合于硅基片表面构成蛋白质芯片,考察了不同表面形貌的硅基片对蛋白质的吸附行为.结果表明:硅基片的表面形貌对蛋白质的吸附行为有很大影响.硅基片经碱蚀刻获得的绒面氧化后因其较大的比表面积、特殊的空间结构及较小的固液接触角θ,对蛋白质具有较强的吸附能力,螯合的蛋白质种类多、丰度大.     

Hot-wire chemical vapor deposition for epitaxial silicon growth on large-grained polycrystalline silicon templates

We investigate low-temperature epitaxial growth of thin silicon films by HWCVD on Si [1 0 0] substrates and polycrystalline template layers formed by selective nucleation and solid phase epitaxy (SNSPE). We have grown 300-nm thick epitaxial layers at 300 °C on silicon [1 0 0] substrates using a high H₂:SiH₄ ratio of 70:1. Transmission electron microscopy confirms that the films are epitaxial with a periodic array of stacking faults and are highly twinned after approximately 240 nm of growth. Evidence is also presented for epitaxial growth on polycrystalline SNSPE templates under the same growth conditions.     

氢等离子体辅助固相晶化多晶硅薄膜的初步研究

提出一种氢等离子辅助固相晶化(hydrogen plasma assisted solid phase crystallization,H-SPC)多晶硅的新颖技术。这一晶化技术能够明显缩短晶化时间,同时有效钝化多晶硅薄膜的缺陷态。首先对氢等离子辅助SPC技术与传统SPC技术进行比较分析,进而研究了晶化过程中各种工艺条件对多晶硅晶化质量的影响并进行了物理机制的初步分析。     

Component redistribution during Nb and In/Nb film growth on single-crystal silicon

The component redistribution during the growth of Nb and In/Nb films on single-crystal silicon has been studied by Rutherford backscattering spectroscopy and X-ray diffraction. The results indicate that magnetron sputtering of indium onto niobium films gives rise to mass transfer across the Nb/Si interface and to niobium and silicon heterodiffusion, accompanied by chemical reactions and the formation of silicides. The likely reason for this is the generation of defects during the magnetron sputtering of indium.     

Low temperature short channel polycrystalline silicon thin film transistors with high reliability for flat panel display

We have investigated a short channel (L ≤ 1 μm) effect on the electrical reliability of the low temperature poly-Si thin film transistors (TFT) on a glass substrate. The threshold voltage of the p-type poly-Si TFT was observed to be decreased due to the drain induced barrier lowering as the channel length decreased. In the n-type poly-Si TFT with a lightly-doped-drain (LDD), the threshold voltage was slightly decreased when a high drain voltage was applied, while the field effect mobility decreased due to the series resistance of the LDD region in the short channel poly-Si TFT. As the temperature increased, the field effect mobility increased about 80% due to the increase of the thermal activated carrier concentration. We have also investigated the degradation of a short channel poly-Si TFT under hot carrier and self-heating stress. After hot carrier stress (V_GS = 2V, V_DS = 15V), the field effect mobility was considerably decreased up to 20% due to the trap state generation induced by the hot carrier. The subthreshold slope and threshold voltage were scarcely degraded. After the self-heating stress (V_GS = V_DS = 15V), the subthreshold slope, mobility, and threshold voltage were degraded. Transfer characteristics measured at the high drain voltage (V_DS = 10V) were shifted to a negative direction because of hole trapping at the backside interface between the polysilicon film and buffer oxide on the glass substrate.     

Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications

The nickel-nanocrystals (Ni-NCs)-embedded silicon nitride acting as a trapping layer has been successfully demonstrated to manipulate the charging and discharging of electrons in a thin film transistor (TFT) for non-volatile memory (NVM) applications. Regarding device performance, with and without Ni-NCs in the stack and under a programming/erasing condition of +/−18 V for 1 s, a better threshold voltage shift of 3.2 V can be reached compared to a shift of 2.0 V for a stack without Ni-NCs. The shift is an index representing the value required to differentiate “0” or “1” states during operation. In this case, the diameter range and number density of Ni-NCs are 5-13 nm and 5.3 × 10¹¹ cm⁻², respectively.     

Determination of bulk and interface density of states in polycrystalline silicon thin film transistors

The aim of our investigation is to determine the bulk and interface density of states in excimer laser annealed polycrystalline silicon thin film transistors (polysilicon TFTs). The exponential energy distribution of the band tail states in the bulk of the polysilicon layer is obtained from analysis of the space charge limited current in n⁺-i-n⁺ structures. The density of traps at the gate oxide/polysilicon interface and the slope of the exponential band tail states in a thin layer adjacent to the channel/gate oxide interface are extracted from low-frequency noise measurements. The experimental results indicate that the degree of disorder is improved in the upper part of the polysilicon layer due to its columnar growth.