Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

Effect of PECVD of SiO2 passivation layers on GaN and InGaP

Thin (200 ) layers of SiO₂ were deposited by plasma enhanced chemical vapor deposition onto GaN and InGaP patterned with transmission line measurement contact pads. The sheet resistance of n-GaN and n- and p-InGaP was measured as a function of N₂O/SiH₄ ratio, rf chuck power, pressure and substrate temperature during the SiO₂ deposition. The sheet resistance ratio before and after the deposition varied from 0.7 to 1.2, reflecting a competition between mechanisms that decrease doping (hydrogen passivation, ion-induced deep traps) and those that increase it (creation of shallow donor states in n-type material through preferential ion of the group V elements, gettering of hydrogen in p-type material). Under most conditions, SiO₂ deposition creates minimal changes to the electrical properties of GaN and InGaP.     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Effect of heating on the structure of Au/GaAs encapsulated with SiO2

The structural effects of heating 1500 Å Au/GaAs (001) encapsulated with 2000 Å of SiO₂ were examined by scanning electron microscopy and X-ray diffraction. It was observed that SiO₂/Au/GaAs (capped) in vacuum up to 500°C remained shiny and gold in color, whereas similar heating of Au/GaAs (uncapped) caused a change of color from shiny gold to dull silver. Furthermore, mass spectroscopy showed that the amount of arsenic vapor evolved was much less for the capped sample. However, X-ray diffraction showed that Au₇Ga₂ formed abundantly in both types of samples after heating at 500°C, though the epitaxial relationship was mainly Au₇Ga₂ (001) GaAs (001) for capped and Au₇Ga₂ (100) GaAs (001) for uncapped. SEM revealed gold-rich aligned rectangular protrusions on the surfaces of SiO₂/Au/GaAs as well as Au/GaAs after heating at 500°C, though the average length of these rectangles was 1.5 μm for the capped sample and 6.7 μm for the uncapped sample. Moreover, new morphological features absent in Au/GaAs were observed in SiO₂/Au/GaAs. These features are a gold-rich maze with a line width of μm and gold-rich protruded lines with a line width of 9 μm. The gold-rich protruded lines were formed by the growth and joining together of some gold-rich aligned rectangular protrusions. The gold-rich maze was observed in SiO₂/Au/GaAs after heating in vacuum, but was not observed in SiO₂/Au/GaAs after heating in nitrogen.     

Contacts materials performances under break arc in automotiveapplications

New materials for electrical contacts have been developed recently, based on AgFeO_x, AgFeRe, AgZnO, and doped AgSnO₂. The work described here aims at evaluating the material transfer characteristics, and the contact resistance behavior, of these materials under break arc in automotive applications (14 V DC, 30-40 A). A comparison is made between these new materials and four reference materials: Ag, AgCdO, AgSnO₂, and AgNi. Four of the new materials appear very promising: AgZnO, AgFeO_x, doped AgSnO₂ io 6, and EMB8. These combine the good transfer performance of AgCdO in inductive load, i.e., in long cathodic arc, with that of AgSnO₂ in resistive load, i.e., in short anodic arc. For all materials, contact resistance is much higher in inductive load (7 mΩ) than in resistive load (1 mΩ). An explanation of the different behaviors of these materials is attempted by means of metallographic analysis     

Electromagnetic interference from discharge phenomena of electriccontacts

The electromagnetic interference (EMI) from steady arc and showering arc electrical discharges was investigated. The experiment was carried out on Ag, Pd, and Ag-Pd alloy contacts under several circuit current conditions. Radiated noise levels were measured at frequencies up to 200 MHz. Experimental results show that the EMI levels from a steady arc, which is generally the phenomenon of the break of a noninductive circuit, are dependent on the composition of contact materials. The EMI levels from a showering arc, which is generally the phenomenon of the break of an inductive circuit, are independent of the composition of contact materials. The EMI from a steady arc is roughly inversely proportional to the frequency in the 0.1-10.0-MHz range, whereas in the 25-200-MHz range, the maximum level of EMI appears at about 70 MHz. The frequency characteristics of EMI from a showering arc are similar to those from a steady arc. The EMIs from these arcs exceed, in part, statutory limits     

Integration of screen-printing and rapid thermal processingtechnologies for silicon solar cell fabrication

For the first time, the potentially cost-effective technologies of rapid thermal processing (RTP) and screen-printing (SP) have been combined into a single process sequence to achieve solar cell efficiencies as high as 14.7% on 0.2 Ω-cm FZ and 14.8% on 3 Ω-cm Cz silicon. These results were achieved without application of a nonhomogeneous (selective) emitter, texturing, or oxide passivation. By tailoring the RTP thermal cycles for emitter diffusion and firing of the screen-printed silver contacts, fill factor values >0.79 were realized on emitters with a sheet resistance (ρ_s ) of ~20 Ω/□ and grid shading <6%. Such high fill factors clearly demonstrate that screen-printed contacts can be fired on extremely shallow RTP emitters (x_j=0.25-0.3 μm) without shunting cells. IQE analysis depicts a strong preference for shallow emitter junction depths to achieve optimal short wavelength response of these unpassivated emitters. In some cases, front contacts were printed through plasma enhanced chemical vapor deposited (PECVD) SiN/SiO₂ dielectrics which prevented the shunting of shallow emitters by serving as partial barriers minimizing the diffusion of metallic species from the contacts. The firing of screen-printed contacts through these PECVD films, achieved the multiple purposes of contact formation, efficient front surface passivation due to annealing of the SiN, and high quality antireflection (AR). Research is presently underway to further optimize the RTP emitter design for screen-printing and develop techniques for implementing selective emitter and oxide passivation technologies for higher efficiency cells     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

Erosion and contact resistance performance of materials for slidingcontacts under arcing

In our previous work, we have investigated copper sliding switching contacts for automotive power applications. In order to improve their reliability, we have studied in this present paper, alternative materials to copper such as silver based materials (Ag, AgSnO₂, AgC, and AgCNi). Their performance was evaluated by measuring mass variations and contact resistance stability during sliding. The contacts are operated in a test machine during 50000 sliding operations, under inductive loads which produce long arcs, or under lamp loads which produce a short arc. In most cases, we have seen a significant wear of the anode compared to the cathode. We believe that the wear process for the sliding contact is the abrasion of the track by a rough contact surface. This roughness is produced and renewed by material transfer because of arcing. Regarding this wear, we show the medium performance of Ag and Cu contacts, while the worst performance is obtained with AgC and AgCNi, which make these latter materials unsuitable. Regarding contact resistance, we have measured low values <1 mΩ for AgC, AgCNi, and Ag. With AgSnO₂ and Cu contacts, the resistance ran reach high values, especially with an inductive load, which make these latter materials unsuitable. Concerning the effect of operating parameters, we show that polarity may emphasize the already poor performance of a high wear anode by disturbing the sliding motion. In addition, contact force and shape size are found to act on material performance: low force and large shape (cylinder) reduce wear and enhance resistance whereas high force and small shape increases wear and lowers contact resistance     

Schottky barrier height of a new ohmic contact NiSi2 to n-type 6H-SiC

We present a new ohmic contact material NiSi₂ to n-type 6H-SiC with a low specific contact resistance. NiSi₂ films are prepared by annealing the Ni and Si films separately deposited on (0 0 0 1)-oriented 6H-SiC substrates with carrier concentrations (n) ranging from 5.8×10¹⁶ to 2.5×10¹⁹ cm⁻³. The deposited films are annealed at 900 °C for 10 min in a flow of Ar gas containing 5 vol.% H₂ gas. The specific contact resistance of NiSi₂ contact exponentially decreases with increasing carrier concentrations of substrates. NiSi₂ contacts formed on the substrates with n=2.5×10¹⁹ cm⁻³ show a relatively low specific contact resistance with 3.6×10⁻⁶ Ω cm². Schottky barrier height of NiSi₂ to n-type 6H-SiC is estimated to be 0.40±0.02 eV using a theoretical relationship for the carrier concentration dependence of the specific contact resistance.     

The unusual electrical erosion of high tungsten content, tungstencopper contacts switching load current in vacuum

The electrical erosion of high tungsten content, tungsten-copper (7-10 wt.% Cu) was investigated. The contacts were placed in a vacuum interrupter envelope with a background pressure of about 10^-6 torr. The contacts switched one half cycle of 60 Hz current per operation. The polarity of the current was changed on each operation. Six contact pairs were investigated. Each pair was subjected to an ever-increasing number of operations: 1 K, 5 K, 10 K, 20 K, 40 K, 50 K, and 60 K. The contact erosion was inferred by measuring the linear position of the moving contact terminal. On completing the electrical testing, the vacuum interrupters were dismantled and the contact surfaces were observed. Unlike the previous work on Ag-WC (50 wt.% Ag) and Cu-Cr (75 wt.% Cu), the W-Cu contacts showed a localized build up of erosion products on the contact surfaces even beginning at 1 K operations. The experiments were repeated switching a unidirectional current i.e., the contacts remained at the same polarity throughout the experiments. Here an anode pip and a cathode crater were formed immediately. The difference in the topographies of these contacts is discussed in terms of the metallographic analysis of the deposits on the contacts, the erosion deposits on the shields surrounding the contacts and the expansion of the vacuum arc     

Extremely high peak specific transconductance AlGaAs/GaAsheterojunction bipolar transistors

Self-aligned AlGaAs/GAs heterojunction bipolar transistors with peak specific transconductances as high as 25 mS/μm² of emitter area are discussed. These are the highest specific transconductances ever reported for a bipolar transistor. These devices, which contain no indium in the emitter, display specific parasitic emitter resistances of less than 1×10^-7 Ω-cm². This low parasitic resistance is attributed to an improved n-type contact technology, in which a molybdenum diffusion barrier and a plasma-enhanced chemical vapor deposition SiO₂ overlayer are used to achieve low specific contact resistivities     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

High-quality MOSFETs with ultrathin LPCVD gate SiO2

MOSFETs and MOS capacitors with ultrathin (65 Å) low-pressure chemical vapor deposition (LPCVD) gate SiO₂ have been fabricated and compared to those with thermal SiO₂ of identical thickness. Results show that the devices with LPCVD SiO₂ have higher transconductance and current drivability, better channel hot-carrier immunity, lower defect density, and better time-dependent dielectric breakdown (TDDB) characteristics than devices with conventional thermal SiO₂     

High current pressure contacts to Ag pads on thin filmsuperconductors

High current, low resistance, nonmagnetic, and nondestructive pressure contacts to Ag pads on YBa₂Cu₃O_7-δ (YBCO) thin film superconductors were developed in this study. The contact resistance reported here includes the resistance of the current lead/Ag pad interface, the Ag pad/YBCO interface, and the bulk resistance of the contact material. This total contact resistance is the relevant parameter which determines power dissipation during critical-current measurements. It was found that regardless of the optimization of the Ag pad/YBCO interface through annealing, a pressure contact can yield a lower total resistance than a soldered contact. The lowest resistance obtained with pressure contacts was 3 μΩ (for a 2×4 mm ² contact). These contacts may be useful for many different high temperature superconductor (HTS) studies where high-current contacts with low heating are needed     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance