低温液体贮槽经济回路的优化设计

分析低温液体贮槽经济回路两种基本形式的工作原理和缺点,阐述实现经济回路应满足的两个条件;提出实现经济回路排液、排气自动切换的3种优化方案,并分析了这3种方案的优点。     

PI controller scheme for charge balance in implantable electrical stimulators

Electrical stimulation has been used in a wide variety of medical implant applications. In all of these applications, due to safety concerns, maintaining charge balance becomes a critically important issue that needs to be addressed at the design stage. It is important that charge balancing schemes be robust to circuit (process) and load impedance variations, and at the same time must also lend themselves to miniaturization. In this communication, simulation studies on the effectiveness of using Proportional Integral (P-I) control schemes for managing charge balance in electrical stimulation are presented. The adaptation of the P-I control scheme to implant circuits leads to two possible circuit realizations in the analog domain. The governing equations for these realizations are approximated to simple linear equations. Considering typical circuit and tissue parameter values and their expected uncertainties, Matlab as well as circuit simulations have been carried out. Simulation results presented indicate that the tissue voltages settle to well below 20% of the safe levels and within about 20 stimulations cycles, thus confirming the validity and robustness of the proposed schemes.     

Designing a programmable analog signal conditioning circuit without loss of measurement range

Programmable analog signal conditioning circuits can be programmed in the field to permit their use in several applications with a variety of sensors with different output signal characteristics. The digital programming of the gain and dc level shift of a conditioning circuit can affect the measurement resolution and cause a reduction in the range of the measuring system in which it is employed. For a specified maximum acceptable loss in the measurement resolution, a procedure for defining and employing the programming values that guarantees the full measurement range is proposed. The proposed methodology takes into account practical implementation considerations and can be employed for designing either discrete or integrated circuits.     

Practical sensorless control for inverter-fed BDCM compressors

Brushless DC motors (BDCMs) possess higher efficiencies than the conventional induction motors and BDCMs have therefore been used widely in inverter-fed compressors. Since the Hall position sensors cannot work well in the high-temperature environment of refrigerants, sensorless control schemes play an important role in the application of inverter-fed BDCM compressors. Sensorless control for actual BDCM compressor is proposed and implemented. First, the sensorless circuits used have been analysed in detail to find the design rules of the circuit parameters for various compressor motors. Then, the limitations of sensorless control are discussed to develop a practical speed controller for BDCM compressors. The developed starting strategy and sensorless algorithms are presented and digitally implemented. Finally, some experimental results are displayed to demonstrate the proposed sensorless speed control for BDCM compressors.     

Low-loss coupler between fiber and waveguide based on silicon-on-insulator slot waveguides

We propose a novel optical fiber-to-waveguide coupler for integrated optical circuits. The proper materials and structural parameters of the coupler, which is based on a slot waveguide, are carefully analyzed using a full-vectorial three-dimensional mode solver. Because the effective refractive index of the mode in a silicon-on-insulator-based slot waveguide can be extremely close to that of the fiber, a highly efficient fiber-to-waveguide coupling application can be realized. For a TE-like mode, the calculated minimum mismatch loss is approximately 1.8 dB at 1550 nm, and the mode conversion loss can be less than 0.5 dB. The discussion of the present state of the art is also involved. The proposed coupler can be used in chip-to-chip communication.     

基于静态特征的硬件木马检测

分析了集成电路全球化设计、制造致使集成电路易被植入硬件木马(HT)从而使其存在遭受恶意攻击隐患的硬件安全形势,以及现有硬件木马检测方法的技术特点,在此基础上提出了一种基于静态特征的硬件木马检测新方法——HTChecker。HTChecker基于硬件木马的静态特征利用子图同构技术来检测木马。与其他的检测方法相比,它可以快速精确地找出已知特征的硬件木马。为了不受限于机器内存的大小,该方法借助图数据库来存储电路,这样它对超大规模的电路也可以进行检测。使用ISCAS’89和OpenCores benchmark电路对HTChecker进行了评估,木马电路被随机地插入到这些电路中。实验结果显示HTChecker可以快速精确地找出木马,并且不需要"Golden Chip"的辅助。HTChecker可以有效地处理实际的VLSI设计。     

Robust end-to-end loss differentiation scheme for transport control protocol over wired/wireless networks

The authors propose a robust end-to-end loss differentiation scheme to identify the packet losses because of congestion for transport control protocol (TCP) connections over wired/wireless networks. The authors use the measured round trip time (RTT) values to determine whether the cause of packet loss is because of the congestion over wired path or regular bit errors over wireless paths. The classification should be as accurate as possible to achieve high throughput and maximum fairness for the TCP connections sharing the wired/wireless paths. The accuracies of previous schemes in the literature depends on varying network parameters such as RTT, buffer size, amount of cross traffic, wireless loss rate and congestion loss rate. The proposed scheme is robust in that the accuracy remains rather stable under varying network parameters. The basic idea behind the scheme is to set the threshold for the classification to be a function of the minimum RTT and the current sample RTT, so that it may automatically adapt itself to the current congestion level. When the congestion level of the path is estimated to be low, the threshold for a packet loss to be classified as a congestion loss is increased. This avoids unnecessary halving of the congestion window on packet loss because of the regular bit errors over the wireless path and hence improves the TCP throughput. When the congestion level of the path is estimated to be high, the threshold for a packet loss to be classified as the congestion loss not to miss any congestion loss is decreased and hence improves the TCP fairness. In ns 2 simulations, the proposed scheme correctly classifies the congestion losses under varying network parameters whereas the previous schemes show some dependency on subsets of parameters.     

Driver circuits for temperature-invariant performance of junction diodes

Different types of driver circuits for the temperature-invariant brightness of light emitting diodes and the RF performance of Schottky barrier diodes, p-i-n diodes and p-n junction diodes are presented. The sensitivities of the proposed driver circuits with ambient temperature, bias voltage and other component variations are presented. Novel techniques are proposed and demonstrated to compensate the performance variation of diode-based circuits due to the temperature sensitivity of the components of driver circuits. The proposed driver circuits eliminate the requirement of conventional temperature compensation techniques with temperature sensors. The driver circuits respond directly to the junction temperature of the diodes itself; thus, there will be no compensation error due to the temperature gradient or self-heating of the diodes. This technique is very simple, accurate and easy to implement.     

Combined methodology for measurement of available bandwidth and link capacity in wired packet networks

Accurate measurement of network parameters such as available bandwidth (ABW), link capacity, delay, packet loss and jitter are used to support and monitor several network functions, for example traffic engineering, quality-of-service (QoS) routing, end-to-end transport performance optimisation and link capacity planning. However, proactive network measurement schemes can impact both the data traffic and the measurement process itself, affecting the accuracy of the estimation if a significant amount of probe traffic is injected into the network. In this work, the authors propose two measurement schemes, one for measuring ABW and the other for measuring link capacity, both of them use a combination of data probe packets and Internet control messaging protocol (ICMP) packets. Our schemes perform ABW and link-capacity measurements in a short time and with a small amount of probe traffic. The authors show a performance study of our measurement schemes and compare their accuracy to those of other existing measurement schemes and also show that the proposed schemes achieve shorter convergence time than other existing schemes and high accuracy.     

Logical scheme improvement for maintaining replicated data in distributed environment

Abstract

Data can be replicated to improve availability and performance in a distributed environment. To ensure the consistency of the replicated data, many schemes have been proposed. Most of these schemes are designed based on the quorum set approach. However, some of them are dominated. Such schemes can be further improved. By using theoretical analysis, we devise a paradigm for refining quorum schemes for managing replicated data. We present two dominating alternatives to a recently proposed high performance scheme.     

Fairness and throughput enhancement based resource allocation scheme for underlay cognitive radio networks

Acquiring good throughput and diminishing interference to primary users (PU) are the main objectives for secondary users in a cognitive radio (CR) network. This paper proposes a centralized subcarrier and power allocation scheme for underlay multi-user orthogonal frequency division multiplexing considering the rate loss and the interference those the PU can tolerate. The main purpose of the proposed scheme is to efficiently distribute the available subcarriers among cognitive users to enhance both the fairness and the throughput performance of the cognitive network while maintaining the QoS of primary users. Simulation results show that the proposed scheme achieves a significantly higher CR network throughput than that of the conventional interference power constraint (IPC) based schemes and provides a significantly enhanced fairness performance. Also, contrary to the conventional IPC based schemes, the proposed scheme is able to significantly increase the achieved throughput as the number of CR users increases.     

Scalable and bijective cells for C-testable iterative logic array architectures

In this study, a novel idea is proposed to test arithmetic circuits with both acceptable number of test patterns (NTP) and hardware overhead (HO). First, highly scalable full adder and full substractor are proposed. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between the NTP and the HO, which is a function of n. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. An iterative logic array (ILA) based on these scalable cells will still be C-testable. Based on the novel bijective and scalable cells, the authors propose C-testable designs for multiplier-accumulator (MAC), N-tap finite impulse response (FIR) filter and matrix multiplication, where the (HO, NTP) pairs with n = 2 are only about (4.87%, 74). For 4 times 4 matrix multiplication, the total test time of the proposed method is only about 0.19% of that with the scan-chain method. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA and save lots of test pins and build-in self-test (BIST) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes the ILA-based DFT schemes more practical, systematic and useful for real-world complex applications.     

On the implementation of an analog ATPG: the nonlinear case

In order to reduce the complexity of the fault diagnosis equations and still retain computational simplicity, a self-testing algorithm has been proposed and implemented on a VMS VAX 11/780 for linear circuits. A prototype implementation of such an algorithm for nonlinear circuits and systems is presented. The proposed analog automatic test program generator (AATPG) for nonlinear circuits and systems is divided into offline and online processes. Unlike the simulation of the pseudocircuits in the linear case, which can be achieved by a matrix/vector multiplication, the circuit simulator SPICE is used to simulate the nonlinear pseudocircuits. The automatic SPICE code generator required for this simulation is presented. The proposed AATPG for nonlinear circuits has been implemented on a VMS VAX 11/780. The actual test can be run in either a fully automatic mode or interactively     

A complete scheme of built-in self-tests (BIST) structure for faultdiagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience     

Disturbance Evaluation in Power System Based on Machine Learning

The operation complexity of the distribution system increases as a large number of distributed generators (DG) and electric vehicles were introduced, resulting in higher demands for fast online reactive power optimization. In a power system, the characteristic selection criteria for power quality disturbance classification are not universal. The classification effect and efficiency needs to be improved, as does the generalization potential. In order to categorize the quality in the power signal disturbance, this paper proposes a multi-layer severe learning computer auto-encoder to optimize the input weights and extract the characteristics of electric power quality disturbances. Then, a multi-label classification algorithm based on rating is proposed to understand the relationship between the labels and identify the various power quality disturbances. The two algorithms are combined to construct a multi-label classification model based on a multi-level extreme learning machine, and the optimal network structure of the multi-level extreme learning machine as well as the optimal multi-label classification threshold are developed. The proposed method can be used to classify the single and compound power quality disturbances with improved classification effect, reliability, robustness, and anti-noise performance, according to the experimental results. The hamming loss obtained by the proposed algorithm is about 0.17 whereas ML-RBF, SVM and ML-KNN schemes have 0.28, 0.23 and 0.22 respectively at a noise intensity of 20 dB. The average precision obtained by the proposed algorithm 0.85 whereas the ML-RBF, SVM and ML-KNN schemes indicates 0.7, 0.77 and 0.78 respectively.     

High input impedance VM-APSs with grounded passive elements

Three new circuit topologies for first-order all-pass filters, each with two variations, realising six new first-order voltage-mode all-pass sections are proposed. Each circuit employs two differential voltage current conveyors and three grounded passive components, ideal for IC implementation. All the circuits possess high input impedance, which is a desirable feature for voltage-mode circuits. As an application, a new quadrature oscillator circuit is realised using one of the proposed all-pass circuits. PSPICE simulations using 0.5 mum CMOS parameters confirm the validity and practical utility of the proposed circuits     

Cross-layer design for block subchannel allocation and admission control in the IEEE 802.16 OFDMA networks

The flexibility of orthogonal frequency-division multiple access (OFDMA) technology necessitates a compromise between spectrum efficiency and quality of service (QoS) in IEEE 802.16 broadband wireless networks. This article proposes a complete solution with the nice feature of adaptive modulation and a coding scheme to provide both delay and loss rate guarantees for real-time services. The proposed method first determines the subframe boundary according to the current downlink and uplink backlogs. To comply with the IEEE 802.16 standard, the proposed method then groups contiguous subchannels and allocates them to proper connections based on the current loss rate and available modulation and coding schemes for each connection. By modeling the aggregated required subchannels as a Gaussian distribution, this study develops a simple admission control algorithm by checking if there are enough resources for a new connection. Simulation results show that the proposed solution can provide QoS guarantee with high spectrum efficiency.     

压电陶瓷振子中的损耗及其对振子特性的影响

压电振子的等效电路形式当考虑损耗时可用两种方法表示：一种方法是不改变相应无损振子的等效电路形式,而将电路参数取为复数;另一种方法是在电路中加入耗能元件。文中分析了压电材料中的损耗现象,并用复数表示有损耗压电振子的各种参数。从压电振子的阻抗方程出发,详细分析了纵效应劝及横效应振动模式振子的谐振频率、频率偏移量与损耗大小、机电耦合系数大小的关系。     

Cascadable adiabatic logic circuits for low-power applications

There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results.     

Improving performance in the OpMiGua hybrid network employing the network layer packet redundancy scheme

The optical migration-capable network with service guarantees hybrid network is a time-divided packet/circuit hybrid network offering absolute performance guarantees and high resource utilisation. Guaranteed service traffic (GST) follows lightpaths receiving absolute priority over statistically multiplexed (SM) traffic. Transmission resources are fully shared by interleaving SM and GST packets, but packet-switched SM packets experience contention, resulting in a packet loss that should be minimised. This article explores a novel bufferless network approach where the performance of the SM class is satisfied by applying packet-level forward error correction (FEC). Two implementation strategies are proposed: RedSM transmitting redundancy packets as SM traffic and RedGST transmitting redundancy packets as low-priority GST traffic. The performance of the schemes is explored analytically and by simulation. For uniform traffic loads, the RedGST scheme shows the best performance of the two, but even at 60% load the RedSM scheme shows packet loss rates (PLRs)close to 1025. Simulations with non-uniform traffic loads illustrate the importance of selecting the optimal redundancy ratio; the failure to do so results in up to two orders of magnitude increase in PLR for the RedGST scheme. A much higher tolerance for traffic variations is the main benefit for the RedSM scheme. In view of the results, both schemes are attractive alternatives to buffered contention resolution techniques.