Highly Flexible MoS(2) Thin-Film Transistors with Ion Gel Dielectrics

Molybdenum disulfide (MoS(2)) thin-film transistors were fabricated with ion gel gate dielectrics. These thin-film transistors exhibited excellent band transport with a low threshold voltage (<1 V), high mobility (12.5 cm(2)/(V·s)) and a high on/off current ratio (10(5)). Furthermore, the MoS(2) transistors exhibited remarkably high mechanical flexibility, and no degradation in the electrical characteristics was observed when they were significantly bent to a curvature radius of 0.75 mm. The superior electrical performance and excellent pliability of MoS(2) films make them suitable for use in large-area flexible electronics.     

Synthesis and characterization of polystyrene brushes for organic thin film transistors

We synthesized and characterized polystyrene brushes on a silicon wafer using surface-initiated atom transfer radical polymerization. The thickness of the polymer brush was controlled by adjusting the reaction time. We investigated monomer conversion as well as the molecular weight and density of the polymer brushes. When the monomer conversion reached 100%, the number-average molecular weight and film thickness reached 135,000 and 113 nm, respectively. The estimated densities of the synthesized polystyrene brushes were in the range 0.34-0.54 chains/nm2, high enough to be categorized in the "concentrated brush" regime. The synthesized polymer brush was used as an insulating layer in an organic thin-film transistor. Organic thin-film transistors were fabricated using pentacene as an active p-type organic semiconductor and a polystyrene brush on a SiO2 layer as a gate dielectric. The pentacene based organic thin-film transistor with the polystyrene brush exhibited a field-effect mobility microFET of 0.099 cm2/(V x s).     

Organic field-effect transistors containing a SiO2 nanoparticle thin film as the gate dielectric

In this article, we report the fabrication of organic field-effect transistors using self-assembled SiO2 as a gate dielectric material and pentacene as a semiconductor. The dielectric layer was self-assembled with 10 layers of SiO2 nanoparticles 45 nm in diameter, and its breakdown field was larger than 0.57 MV/cm. Being a low-cost and low-temperature process, the layer-by-layer self-assembly is particularly suitable for organic field-effect transistor fabrication. The pentacene was thermally evaporated on the substrate under high vacuum at the room temperature. The fabricated transistor has a threshold voltage of 0.3 V, field-effect mobility of 0.05 cm2/Vs, and slope of 1.4 V/decade.     

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.     

Investigation of self-assembled monolayer treatment on SiO2 gate insulator of poly(3-hexylthiophene) thin-film transistors

We have investigated self-assembled monolayer (SAM) treatment on SiO₂ gate insulator of poly(3-hexylthiophene) (P3HT) thin-film transistor (TFT), and demonstrated a correlation between mobility and surface free energy of the insulator. The device with lower surface free energy shows higher mobility. The docosyltrichlorosilane (DCTS)-treated device exhibits the best performance among the various SAM-treated devices examined. Field-effect mobility, on/off ratio and threshold voltage of the DCTS-treated P3HT TFT were 0.015 cm²/Vs, >10⁵ and −14 V, respectively.     

Effects of the surface treatment with monolayers of twisted biaryls on the efficiency of pentacene thin-film transistors

A pentacene thin-film transistor (TFT) was fabricated on a SiO2 gate insulator modified with twisted biaryls. The biaryl monolayer, in particular a binaphthyl (BN) monolayer, is amorphous surface where the naphthalene rings are randomly oriented with no lateral order because of their rigid, twisted, and asymmetric shape. When the BN monolayer was used for the surface treatment of SiO2, large grains were obtained in the early stages of the pentacene crystal growth. The pentacene TFT had a field effect mobility (microm) in excess of 0.4 cm2/Vs and an on/off ratio greater than 10(5). The surface treatment improved the mobility of the pentacene TFT by a factor of 50% compared with non-treated devices. The morphology of the semiconductor layer was investigated using atomic force microscopy (AFM) and X-ray diffraction (XRD).     

Bandlike transport in strongly coupled and doped quantum dot solids: a route to high-performance thin-film electronics

We report bandlike transport in solution-deposited, CdSe QD thin-films with room temperature field-effect mobilities for electrons of 27 cm(2)/(V s). A concomitant shift and broadening in the QD solid optical absorption compared to that of dispersed samples is consistent with electron delocalization and measured electron mobilities. Annealing indium contacts allows for thermal diffusion and doping of the QD thin-films, shifting the Fermi energy, filling traps, and providing access to the bands. Temperature-dependent measurements show bandlike transport to 220 K on a SiO(2) gate insulator that is extended to 140 K by reducing the interface trap density using an Al(2)O(3)/SiO(2) gate insulator. The use of compact ligands and doping provides a pathway to high performance, solution-deposited QD electronics and optoelectronics.     

High-performance single layered WSe₂ p-FETs with chemically doped contacts

We report high performance p-type field-effect transistors based on single layered (thickness, ～0.7 nm) WSe(2) as the active channel with chemically doped source/drain contacts and high-κ gate dielectrics. The top-gated monolayer transistors exhibit a high effective hole mobility of ～250 cm(2)/(V s), perfect subthreshold swing of ～60 mV/dec, and I(ON)/I(OFF) of >10(6) at room temperature. Special attention is given to lowering the contact resistance for hole injection by using high work function Pd contacts along with degenerate surface doping of the contacts by patterned NO(2) chemisorption on WSe(2). The results here present a promising material system and device architecture for p-type monolayer transistors with excellent characteristics.     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

High carrier mobility in single ultrathin colloidal lead selenide nanowire field effect transistors

Ultrathin colloidal lead selenide (PbSe) nanowires with continuous charge transport channels and tunable bandgap provide potential building blocks for solar cells and photodetectors. Here, we demonstrate a room-temperature hole mobility as high as 490 cm(2)/(V s) in field effect transistors incorporating single colloidal PbSe nanowires with diameters of 6-15 nm, coated with ammonium thiocyanate and a thin SiO(2) layer. A long carrier diffusion length of 4.5 μm is obtained from scanning photocurrent microscopy (SPCM). The mobility is increased further at lower temperature, reaching 740 cm(2)/(V s) at 139 K.     

Epitaxial graphene transistors: enhancing performance via hydrogen intercalation

We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.     

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO₂ gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO₂ surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO₂ surface.     

Low voltage, hysteresis free, and high mobility transistors from all-inorganic colloidal nanocrystals

High-mobility solution-processed all-inorganic solid state nanocrystal (NC) transistors with low operation voltage and near-zero hysteresis are demonstrated using high-capacitance ZrO(x) and hydroxyl-free Cytop gate dielectric materials. The use of inorganic capping ligands (In(2)Se(4)(2-) and S(2-)) allowed us to achieve high electron mobility in the arrays of solution-processed CdSe nanocrystals. We also studied the hysteresis behavior and switching speed of NC-based field effect devices. Collectively, these analyses helped to understand the charge transport and trapping mechanisms in all-inorganic NCs arrays. Finally, we have examined the rapid thermal annealing as an approach toward high-performance solution-processed NCs-based devices and demonstrated transistor operation with mobility above 30 cm(2)/(V s) without compromising low operation voltage and hysteresis.     

Control of carrier density by self-assembled monolayers in organic field-effect transistors

Organic thin-film transistors are attracting a great deal of attention due to the relatively high field-effect mobility in several organic materials. In these organic semiconductors, however, researchers have not established a reliable method of doping at a very low density level, although this has been crucial for the technological development of inorganic semiconductors. In the field-effect device structures, the conduction channel exists at the interface between organic thin films and SiO(2) gate insulators. Here, we discuss a new technique that enables us to control the charge density in the channel by using organosilane self-assembled monolayers (SAMs) on SiO(2) gate insulators. SAMs with fluorine and amino groups have been shown to accumulate holes and electrons, respectively, in the transistor channel: these properties are understood in terms of the effects of electric dipoles of the SAMs molecules, and weak charge transfer between organic films and SAMs.     

High-kappa dielectrics for advanced carbon-nanotube transistors and logic gates

The integration of materials having a high dielectric constant (high-kappa) into carbon-nanotube transistors promises to push the performance limit for molecular electronics. Here, high-kappa (approximately 25) zirconium oxide thin-films (approximately 8 nm) are formed on top of individual single-walled carbon nanotubes by atomic-layer deposition and used as gate dielectrics for nanotube field-effect transistors. The p-type transistors exhibit subthreshold swings of S approximately 70 mV per decade, approaching the room-temperature theoretical limit for field-effect transistors. Key transistor performance parameters, transconductance and carrier mobility reach 6,000 S x m(-1) (12 microS per tube) and 3,000 cm2 x V(-1) x s(-1) respectively. N-type field-effect transistors obtained by annealing the devices in hydrogen exhibit S approximately 90 mV per decade. High voltage gains of up to 60 are obtained for complementary nanotube-based inverters. The atomic-layer deposition process affords gate insulators with high capacitance while being chemically benign to nanotubes, a key to the integration of advanced dielectrics into molecular electronics.     

Behavior of pentacene initial nucleation on various dielectrics and its effect on carrier transport in organic field-effect transistor

The influence of dielectric surface energy on the initial nucleation and the growth of pentacene films as well as the electrical properties of the pentacene-based field-effect transistors are investigated. We have examined a range of organic and inorganic dielectrics with different surface energies, such as polycarbonate/SiO2, polystyrene/SiO2, and PMMA/SiO2 bi-layered dielectrics and also the bare SiO2 dielectric. Atomic force microscopy measurements of sub-monolayer and thick pentacene films indicated that the growth of pentacene film was in Stranski-Kranstanow growth mode on all the dielectrics. However, the initial nucleation density and the size of the first-layered pentacene islands deposited on different dielectrics are drastically influenced by the dielectric surface energy. With the increasing of the surface energy, the nucleation density increased and thus the average size of pentacene islands for the first mono-layer deposition decreased. The performance of fabricated pentacene-based thin film transistors was found to be highly related to nucleation density and the island size of deposited Pentacene film, and it had no relationship to the final particle size of the thick pentacene film. The field effect mobility of the thin film transistor could be achieved as high as 1.38 cm2Ns with on/off ratio over 3 x 10(7) on the PS/SiO2 where the lowest surface energy existed among all the dielectrics. For comparison, the values of mobility and on/off ratio were 0.42 cm2Ns and 1 x 10(6) for thin film transistor deposited directly on bare SiO2 having the highest surface energy.     

Modeling novel double-in-plane gate electric-double-layer thin-film and nanoscale transistors

A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thin-film transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm(2)). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner.     

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (～4.1 eV) compared to that of a pristine Au electrode (～4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ～0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ～0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ～12 kHz) based on a solution-processed ambipolar polymer are demonstrated.     

Low-voltage p- and n-type organic self-assembled monolayer field effect transistors

We report on p- and n-type organic self-assembled monolayer field effect transistors. On the base of quaterthiophene and fullerene units, multifunctional molecules were synthesized, which have the ability to self-assemble and provide multifunctional monolayers. The self-assembly approach, based on phosphonic acids, is very robust and allows the fabrication of functional devices even on larger areas. The p- and n-type transistor devices with only one molecular active layer were demonstrated for transistor channel lengths up to 10 μm. The monolayer composition is proven by electrical experiments and by high-resolution transmission electron microscopy, electron energy loss spectroscopy, XPS, and AFM experiments. Because of the molecular design and the contribution of isolating alkyl chains to the hybrid dielectric, our devices operate at low supply voltages (-4 V to +4 V), which is a key requirement for practical use and simplifies the integration in standard applications. The monolayer devices operate in ambient air and show hole and electron mobilities of 10(-5) cm(2)/(V s) and 10(-4) cm(2)/(V s) respectively. In particular the n-type operation of self-assembled monolayer transistors has not been reported before. Hereby, structure-property relations of the SAMs have been studied. Furthermore an approach to protect the sensitive C(60) from immediate degradation within the molecular design is provided.     

Low-voltage organic field-effect transistors (OFETs) with solution-processed metal-oxide as gate dielectric

In this study, low-voltage copper phthalocyanine (CuPc)-based organic field-effect transistors (OFETs) are demonstrated utilizing solution-processed bilayer high-k metal-oxide (Al(2)O(y)/TiO(x)) as gate dielectric. The high-k metal-oxide bilayer is fabricated at low temperatures (< 200 °C) by a simple spin-coating technology and can be controlled as thin as 45 nm. The bilayer system exhibits a low leakage current density of less than 10(-5) A/cm(2) under bias voltage of 2 V, a very smooth surface with RMS of about 0.22 nm and an equivalent k value of 13.3. The obtained low-voltage CuPc based OFETs show high electric performance with high hole mobility of 0.06 cm(2)/(V s), threshold voltage of -0.5 V, on/off ration of 2 × 10(3) and a very small subthreshold slope of 160 mV/dec when operated at -1.5 V. Our study demonstrates a simple and robust approach that could be used to achieve low-voltage operation with solution-processed technique.