Effects of burn-in stressing on radiation response of power VDMOSFETs

The effects of pre-irradiation burn-in stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of power MOSFETs. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects. The buildup of oxide-trapped charge appeared to be almost independent of device pre-irradiation stress, while the buildup of interface traps was somewhat less pronounced in stressed devices. Passivation of interface-trap precursors due to diffusion of hydrogen related species (originating either from package inside or gate oxide adjacent structures) from the bulk of the oxide towards the interface has been proposed as a mechanism responsible for the suppressed interface-trap buildup in pre-irradiation stressed devices.     

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO₂/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.     

Effects of high electric field and elevated-temperature bias stressing on radiation response in power VDMOSFETs

The effects of pre-irradiation high electric field and elevated-temperature bias stressing on radiation response of power VDMOSFETs have been investigated. Compared to unstressed devices, larger irradiation induced threshold voltage shift and mobility reduction in high electric field stressed devices have been observed, clearly demonstrating inapplicability of electrical stressing for radiation hardening of power MOSFETs. On the other hand, larger irradiation induced threshold voltage shift in elevated-temperature bias stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of these devices. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects.     

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs have been investigated to get better insight into the NBTI phenomena. Negative bias annealing does not affect stress-induced degradation significantly, whereas either zero or positive bias annealing removes the portion of stress-induced oxide-trapped charge while creating additional interface traps. The removable component of stress-induced oxide-trapped charge is found to decrease, and influence of external bias on annealing phenomena weakens with duration of preceding stressing, suggesting that extended stress moves the trapped charge to energetically deeper oxide traps, which are more difficult to anneal.     

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.     

Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N⁻channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO₂/Si barrier.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Mechanisms of positive gate-bias stress induced instabilities in CMOS transistors

Increase of positive gate oxide charge and interface trap densities has been shown to be responsible for positive gate-bias stress induced instabilities of threshold voltage and gain factor in Al-gate and Si-gate CMOS transistors. The electron tunneling from trivalent-silicon and/or oxygen-vacancy defects into the oxide conduction band has been established as a mechanism of the positive gate oxide charge creation. The creation of interface traps, appearing due to interfacial trivalent silicon atoms, has been related to the reaction between interfacial Si-H or Si-OH groups and the positive gate oxide charge built up close to the oxide-silicon interface.     

Post-irradiation formation of Si-SiO2 interface states in a hydrogen atmosphere at room temperature

Si MOSFETs were irradiated with x-rays and then exposed to various partial pressures of H₂ at either room temperature or 125 °C. The number of interface traps and the net positive oxide trapped charged were measured during the hydrogen exposure using spectroscopic charge pumping techniques. During the hydrogen exposure the gate electrode was held at a positive bias to maintain a field of 0.65 MV/cm across the gate oxide. It was found that during the room temperature hydrogen exposure the number of interface traps increased by a factor of about two. The change in the oxide trapped charge during hydrogen exposure indicated that the decrease in the number of positively charged oxide traps was approximately the same as the increase in the number of interface traps. The time evolution and bias dependence of these changes are explained by a model that we previously proposed. In this model positively charged radiation induced defects in the oxide crack the H₂ to form H⁺. Under positive gate bias the H⁺ then drifts to the Si-SiO₂ interface where it forms an interface state, while at the same time removing positive charge from the oxide.     

The generation and characterization of electron and hole trapscreated by hole injection during low gate voltage hot-carrier stressingof n-MOS transistors

Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V_g⩽V_d/4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, σ(1)≈3×10^-15 and σ(2)≈3×10^-16 cm²     

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs

The influence of parasitic charge at the Si–SiO₂ interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25?nm is studied. The results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunnelling current.     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Hole traps in silicon dioxides. Part I. Properties

As the downscaling of gate oxides continues, trap density in the oxide bulk will reduce, but positive charges formed near to the SiO/sub 2//Si interface become relatively important. For gate oxides used in industry, hole trapping is the most important process for positive charge formation. Apart from as-grown hole traps, we recently reported that new hole traps were generated by electrical stresses. Information on these hole traps, however, is still limited. In part I of this work, properties of both generated and as-grown hole traps are investigated. For the first time, it will be clearly shown that generated hole traps consist of two components; cyclic positive charges (CPC) and antineutralization positive charges (ANPC). The charging and discharging rates of CPC are similar, while the neutralization of ANPC is much more difficult than its charging. Differences between them are also observed in generation kinetics and dependence on measurement temperature. Efforts will be made to explain their differences in terms of energy levels and to link them with positive charges reported in earlier works. We will also show that as-grown traps, regardless their distance from the interface, are not responsible for either ANPC or CPC. This is to say that generated hole traps are not the same as as-grown traps and their differences will be highlighted. In part II, hole trap generation mechanisms will be investigated.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

Studies of the quality of GdSiO-Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C-V, I-V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C-V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.