一种用于光通信的新型时钟提取电路设计

提出了一种采用数据转换跟踪环的时钟提取电路设计方法,介绍了这种新环路的设计结构及工作原理,并对环路性能进行了理论分析和仿真.分析和仿真表明,该电路具有很好的跟踪性能,信噪比较低时可以保持锁定状态,有突发相位抖动出现时可快速进入锁定.可以用于光纤通信系统中.     

A 30-MHz hybrid analog/digital clock recovery circuit in 2-μmCMOS

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process     

时钟提取与抖动衰减数字锁相环设计研究

文章简要介绍了数字锁相环(DPLL)的工作原理,重点提出了用于V5接口芯片中的时钟提取锁相环和抖动衰减锁相环的设计,并对其进行了分析．     

A self correcting clock recovery circuit

Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.     

A self correcting clock recovery curcuit

Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.     

Coding, decoding, and recovery of clock synchronization in digital multiplexing system

High-speed broadband digital communication networks rely on digital multiplexing technology where clock synchronization, including processing, transmission, and recovery of the clock, is the critical technique. This paper interprets the process of clock synchronization in multiplexing systems as quantizing and coding the information of clock synchronization, interprets clock justification as timing sigma-delta modulation (T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification as quantization error. As a result, decreasing the quantization error is equivalent to decreasing the jitter of justification. Using this theory, the paper studies the existing jitter-reducing techniques in transmitters and receivers, presents some techniques that can decrease the quantization error (justification jitter) in digital multiplexing systems, and presents a new method of clock recovery.     

The jitter time-stamp approach for clock recovery of real-timevariable bit-rate traffic

When multimedia streams arrive at the receiver, their temporal relationships may be distorted due to jitter. Assuming the media stream is packetized, the jitter is then the packet's arrival time deviation from its expected arrival time. There are various ways to reduce jitter, which include synchronization at the application layer, or synchronization at the asynchronous transfer mode (ATM) adaptation layer (AAL). The new source rate recovery scheme called jitter time-stamp (JTS) provides synchronization at the ATM adaptation layer 2 (AAL2) which is used to carry variable bit-rate traffic such as compressed voice and video. JTS is implemented, and experiments have shown that it is able to recover the source rate     

一种10ps以下时钟偏差的纯数字电路分频器设计

本文对一款常用任意整数分频器进行改进,提出了一种纯数字、低时钟偏差、可获得任意整数分频结果的时钟分频器设计方案.该分频器由计数器与输出锁存器构成,通过调节逻辑结构与线延迟,完全平衡各时钟传播路径,大幅降低时钟偏差.仿真结果表明,在TSMC 0.13μm CMOS工艺下,当输入时钟频率在600MHz时,时钟偏差可控制在10ps以内.该分频器还包含自测电路,可判断时钟偏差是否满足要求.     

A digital approach to an FM exciter

A digital approach to an FM exciter is presented that provides several advantages over previous analog techniques. This approach, called direct digital frequency modulation (DDFM), is centered around a direct digital synthesis (DDS) chip which allows true digital generation of the FM signal. The DDS chip is a perfectly linear modulator with superior phase-noise characteristics over the current analog voltage-controlled oscillator (VCO) approach. The DDS modulator drives a low-noise phase-locked loop (PLL) which allows upconversion to any FM channel without manual tuning. The exciter demonstrates superior microphonics immunity by separating the frequency tuning from the modulation path, thus allowing wider PLL bandwidths. The exciter can accept either the existing composite analog format or can interface with future digital sources     

A digital signal processing approach to interpolation

In many digital signal precessing systems, e.g., vacoders, modulation systems, and digital waveform coding systems, it is necessary to alter the sampling rate of a digital signal Thus it is of considerable interest to examine the problem of interpolation of bandlimited signals from the viewpoint of digital signal processing. A frequency dmnain interpretation of the interpolation process, through which it is clear that interpolation is fundamentally a linear filtering process, is presented, An examination of the relative merits of finite duration impulse response (FIR) and infinite duration impulse response (IIR) digital filters as interpolation filters indicates that FIR filters are generally to be preferred for interpolation. It is shown that linear interpolation and classical polynomial interpolation correspond to the use of the FIR interpolation filter. The use of classical interpolation methods in signal processing applications is illustrated by a discussion of FIR interpolation filters derived from the Lagrange interpolation formula. The limitations of these filters lead us to a consideration of optimum FIR filters for interpolation that can be designed using linear programming techniques. Examples are presented to illustrate the significant improvements that are obtained using the optimum filters.     

A gallium-arsenide digital phase shifter for clock and controlsignal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components     

A generalized series approach to MR spectroscopic imaging

The problem of precise spatial localization of spectral information in magnetic resonance (MR) spectroscopic imaging is addressed. A novel method, called GSLIM (generalized spectral location by imaging), is proposed to make possible the marriage of high-resolution proton imaging with spectroscopic imaging and localization. This method improves on the conventional Fourier series inversion method used in chemical shift imaging (CSI) and the compartmental modeling method used in SLIM by using a generalized series framework for optimal representation of the spectral function. In this way, a priori information extracted from proton imaging can be used, as in SLIM, and the robustness and data consistency of CSI are also retained. Simulation results show that GSLIM can significantly reduce spectral leakage in CSI and inhomogeneity errors in SLIM. It can also reveal compartmental inhomogeneities, and can easily be extended to handle other a priori constraints when necessary. This approach, with some further development, may achieve an optimal combination of sensitivity, quantitative accuracy, speed, and flexibility for in vivo spectroscopy.     

A generalized space-mapping tableau approach to device modeling

A comprehensive framework to engineering device modeling, which we call generalized space mapping (GSM) is introduced in this paper. GSM permits many different practical implementations. As a result, the accuracy of available empirical models of microwave devices can be significantly enhanced. We present three fundamental illustrations: a basic space-mapping super model (SMSM), frequency-space-mapping super model (FSMSM) and multiple space mapping (MSM). Two variations of MSM are presented: MSM for device responses and MSM for frequency intervals. We also present novel criteria to discriminate between coarse models of the same device. The SMSM, FSMSM, and MSM concepts have been verified on several modeling problems, typically utilizing a few relevant full-wave electromagnetic simulations. This paper presents four examples: a microstrip line, a microstrip right-angle bend, a microstrip step junction, and a microstrip shaped T-junction, yielding remarkable improvement within regions of interest     

数字钟电路的设计

数字钟是采用数字电路实现的计时装置,主要介绍了555定时器构成的多谐振荡电路作为时钟源的数字钟的基本组成和工作原理。电路元件大多为中小规模集成电路,是现下较为流行的数字钟的制作方案。     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

A 155-MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth