双向可控硅静电防护器件中p型井对静电性能影响的研究

基于0.18μm Bipolar CMOS-DMOS(BCD)工艺,研究讨论了双向可控硅静电防护器件中p型井（PW）位置对器件维持电压以及鲁棒性的静电性能影响,可用于高压静电放电（ESD）保护。利用二维器件仿真平台和传输线脉冲测试系统（TLP）,预测和验证了PW的尺寸在高压工艺下对双向对称可控硅性能的影响。测量结果表明,在不增加器件面积的情况下,通过高压对称DDSCR器件PW层次的左侧边界位置缩进,所得的DDSCR＿PW器件的正向维持电压（Vh）虽然从30.15 V降低到15.63 V,反向维持电压从26.15 V降低到16.85 V,但与高压对称DDSCR器件相比,高压对称DDSCR＿PW器件具有提升失效电流的优点,其正向失效电流从6.68 A增加到18.22 A,反向失效电流从7.07 A增加到9.92A,论文阐述了产生此现象的原因。     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

保护环版图结构对ESD防护器件耐压能力的影响

基于华润上华0.5 μm双极-CMOS-DMOS (BCD)工艺设计制备了不同保护环分布情况下的叉指型内嵌可控硅整流器的横向扩散金属氧化物半导体(LDMOS-SCR)结构器件,并利用传输线脉冲(TLP)测试比较静电放电(ESD)防护器件的耐压能力.以LDMOS-SCR结构为基础,按照16指、8指、4指和2指设置保护环,形成4种不同类型的版图结构.通过器件的直流仿真分析多指器件的开启情况,利用传输线脉冲测试对比不同保护环版图结构的耐压能力.仿真和测试结果表明,改进后的3类版图结构相对于普遍通用的第一类版图结构,二次击穿电流都有所提升,其中每8指设置一个保护环的版图结构二次击穿电流提升了76.36％,其单位面积的鲁棒性能也最好,为相应工艺设计最高耐压值的ESD防护器件提供了参考结构和方法.     

双向可控硅器件在片上静电防护中的应用

设计了一种用于芯片静电放电(ESD)防护的双向可控硅(DDSCR)器件.该器件具有对称性或非对称性骤回I-V特性,可以用于多种应用场合.器件的最优静电防护性能达到94 V/μm.简洁的器件结构用于输入/输出保护,对内部电路的寄生效应小,人体模型ESD测试达到耐压等级3(超过4 kV).在多电源芯片的静电防护中,双向可控硅器件可克服普通器件不能胜任的多模式静电事件的发生.首次提出了双向可控硅器件在高速多媒体接口中静电防护和反向驱动保护的应用.     

一种非对称双向可控硅静电防护器件的设计

非对称双向可控硅(ADDSCR)是在考虑了保护环结构之后,为使I-V特性曲线对称而设计的非对称结构,但是其维持电压较低,容易闩锁.为了提高传统ADDSCR的维持电压,基于0.18μm BCD工艺,设计维持电压高的HHVADDSCR.经TCAD仿真,证明HHVADDSCR具有高维持电压,避免了闩锁,且器件适用于传输电平在...     

一种用于低压防护的新型闩锁免疫双向可控硅

针对传统片上静电放电(ESD)防护器件双向可控硅(DDSCR)的低维持电压特性,设计了一种内嵌多MOS管的新型DDSCR。通过多MOS管组成的旁路通路进行分流,能够增强反偏结电场,从而提高器件抗闩锁能力。基于TCAD进行仿真,模拟TLP测试结果表明,与NLVT_DDSCR相比,新型器件的触发电压基本保持不变,维持电压从3.50 V提高到5.06 V,通过拉长关键尺寸D5,可将器件维持电压进一步提高到6.02 V,适用于电源轨为5 V的低压芯片防护。     

测试双向可控硅输出电压波形对称性的简便方法

重点介绍使用万用表测量双向可控硅输出电压波形对称性的简便方法。     

ESD防护器件中SCR结构开启速度的优化与分析

针对静电放电(ESD)防护过程中ESD防护器件开启速度慢、易引起栅氧击穿或电路烧毁的问题,提出了一种可控硅(SCR)结构的ESD防护器件开启速度的优化方法。首先,基于0.35μm Bipolar-CMOS-DMOS(BCD)工艺制备了P~+浮空和P~+接地SCR结构器件,通过分析阱间距对P~+接地SCR影响,获知当阱间距增至8.68μm时,器件开启速度快且过击穿电压低。其次,对比分析关键尺寸参数相同条件下P~+接地与P~+浮空SCR器件ESD防护性能,传输线脉冲测试结果表明,P~+浮空比P~+接地SCR开启速度更快。最后,通过进一步优化P~+浮空SCR器件特征参数,器件开启速度可提高约17.70%。TCAD仿真结果证明:与P~+接地SCR相比,P~+浮空SCR的电流密度分布较均匀,且导通时间短,有利于提高开启速度,因此P~+浮空SCR器件更适用于高速集成电路的ESD防护。     

深亚微米工艺中场氧器件静电防护能力的研究

研究了FOD在输入、输出和电源箝位部分ESD的工作特点,在0.18μm5V EEPROM CMOS工艺下流片、测试并分析了针对输入、输出和电源箝位的三种主流的ESD保护FOD器件,通过传输线脉冲测试仪的测量,重点分析了特征尺寸对器件ESD特性的影响及其设计方法。结果表明:影响FOD的ESD性能的主要因素是沟道长度、漏极长度和漏极接触孔到有源区的距离;增加沟道长,可适当提高FOD的ESD开启电压,但是会降低ESD防护性能;增加FOD的漏极长度和漏极接触孔到有源区的距离,可以提高FOD的ESD防护性能。提出了一种新型的浮体多晶硅岛屿型FOD结构,该结构不但结构简单,而且具有良好的ESD防护性能。     

Robust PIN photodiode with a guard ring protection structure

A guard ring (GR) structure is used to protect a planar InGaAs pin photodiode. The human body model (HBM) measurement results show that a photodiode with a GR, which is shorted to the cathode, is able to withstand an electrostatic discharge (ESD) threshold voltage of up to 200 V, whereas a similar photodiode without a GR structure can only withstand 50 V ESD threshold voltage. The capacitance and bandwidth measurement results show that the GR has negligible negative effects on the pin diode performance.     

New fast turn-on speed SCR device for electrostatic discharge protection

A new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed to improve the turn-on speed for electrostatic discharge (ESD) protection. The turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR, and the VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the VSCRs with the VLBD structure is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.     

Design of novel DDSCR with embedded PNP structure for ESD protection* Xiuwen Bi (毕秀文), Hailian Liang (梁海莲), Xiaofeng Gu (顾晓峰)?, Long Huang (黄龙)

通过在常规双向可控硅器件(DDSCR)内部嵌入一个PNP结构,提出了一种新型的静电防护(ESD)器件DDSCR-PNP,以提高器件的维持电压(Vh),降低闩锁风险。首先,分析了DDSCR-PNP器件的工作机理,理论分析表明,内嵌PNP结构(PNP_2)使器件具有很好的电压箝位能力。然后,基于0.35 μm Bipolar-CMOS-DMOS工艺制造了实验器件,并利用Barth 4002传输线脉冲测试系统进行了分析。测试结果证明了DDSCR-PNP的Vh比传统DDSCR高得多,而且通过调节P阱宽度可进一步增加Vh。然而,当P阱宽度超过12 μm时,DDSCR-PNP的漏电流(IL)出现明显波动。最后,利用Sentaurus仿真分析了影响Vh和IL的原因。结果表明,横向PNP_2有助于提高Vh并降低IL,但其作用随着P阱宽度的增大而减弱,导致IL随之增大。这种新型的DDSCR-PNP器件为高压集成电路的ESD防护提供了一种有效的解决方案。     

Effect of shunt capacitance on tapered distributed RC network characteristics

The effect of stray shunt capacitance on the characteristics of distributed RC networks, particularly in MOS integrated form, is considered. It is shown that the expected superiority of the tapered network over the uniform network in giving lower attenuation for a given phase shift is unlikely to be physically realisable because of the greater sensitivity of the former to the effect of stray shunt capacitance.     

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

In this paper, we show how latch-up guard rings, surrounding electrostatic discharges (ESD) protection devices, can reduce the overall performance of the ESD protection scheme. This issue is addressed by TCAD simulation and experimental results. Design guidelines to cope with this problem are proposed.     

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

High reliability electronic devices need to sustain thousands of electrostatic discharge (ESD) stresses during their lifetime. In this paper, it is demonstrated that repetitive ESD stresses on a protection device such as a bidirectional diode induce progressive defects into the silicon bulk. With “Sirtl etch” failure analysis technique, the defects could be localized quite precisely at the peripheral in/out junctions. The degradation mechanisms during repetitive IEC 61000-4-2 pulses have been investigated on a protection diode with the objective of improving the design for sustaining 1000 pulses at 10 kV level.     

关于电子工程的静电保护研究

本文在此基础上,将突破口选取成电气工程和电子工程的介绍,并且还将其侧重点放在解释产生静电与在电子工程过程中所导致的各种影响,最终立足于这些不同程度的影响,提出各种在电子工程中防护静电的殴,从而开业为电子工程呈现更加安全与稳定的发展提供必要的保证.     

Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device

In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.     

Elimination of the guard ring in uniform avalanche photodiodes

A conventionalp^{+}-n(orn^{+}-p) planar avalanche photodiode with a 10^-4cm²active area has ∼2.5 × 10^-4cm²total area because of its protecting guard ring and has a series resistance of ∼50 to 100 ohms. For narrow-band applications, multiplications greater than 10 are necessary to equal the available output power of a conventional nonavalanchingp-i-nphotodiode. In broad-band applications, significant multiplications are necessary to compete favorably with thep-i-nwhen the active area is less than 10^-4cm²or when the signal frequency is > 1 GHz. Ap-n^{+}planar structure is discussed that eliminates the need for a guard ring because positive junction curvature occurs on the high-resistivity side. Thep-n^{+}diodes can be designed to have resistances (Rs∼2 ohms), capacitances (C < 1 pf), and RC cutoff frequencies (fco>100 GHz) equivalent to those of thep-i-nand to have uniform multiplication as well. Closer array spacings can be achieved than with the guard ring structure, as well as higher effective quantum efficiencies in the avalanche mode. Practical realization of thep-n^{+}structure has been achieved in silicon by a combination of epitaxial and doped-oxide processing. Seven-mil-diameter junctions with high breakdown voltage (110 V) and uniform avalanche properties have been constructed.