一种硅衬底镂空结构的圆形射频微电感

利用MEMS工艺以及硅的湿法刻蚀工艺制作了一种硅衬底镂空结构的圆形射频微电感，并研究了硅衬底背面减薄对射频微电感性能的影响，结果表明：微电感硅衬底经过局部刻蚀减薄后其自谐振频率上升，电感量的频率稳定性提高，而其最大Q值下降。     

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.     

激光-MIG复合焊背面熔宽的检测

对接焊中,背面熔宽最直接地反映了熔透状态.为获取CO2激光-MIG复合焊背面熔宽的信息,本文采用视觉传感器获得了熔池背面清晰的图像,并运用图像增强及边界追踪的算法提取了熔池边缘,通过多帧图像取平均值的方法确定了输出熔池宽度的最佳位置,从而成功确定了熔池的背面宽度.     

New latchup mechanism in complementary bipolar power ICs triggered by backside die attach Glue

It is shown that in complementary bipolar power ICs latchup can be caused by a thyristor formed by the V-PNP power transistor at the frontside of the die and a Ag-filled glue die attach at the backside of the die (used to provide a good thermal contact between the die and the Cu-heatsink. The thyristor is triggered by saturation of the V-PNP power transistors or by forward biasing the backside diode between Ag-filled glue and p-type silicon. The effect is strongly temperature dependent. It can be eliminated by either leaving the backside floating or by applying backside metallization. Consequences for latchup qualification testing are discussed.     

背面多孔硅对SIMOX中铜杂质的吸除作用

在SIMOX材料的背面成功地制备了多孔硅层,再在正面故意注入1×1015cm-2剂量的铜杂质。经900℃退火,二次离子质谱（SIMS）测试表明钢杂质能穿过理层SiO2并在背面多孔硅处富集。用剖面投射电子显微镜（XTEM）分析了埋层SiO2和背面多孔硅层的微观结构,背面多孔硅层及其多孔硅层同硅衬底之间“树技状”的过渡区被认为是铜杂质有效的吸除中心。     

Advanced backside failure analysis in 65 nm CMOS technology

Due to reducing size of elementary devices, increasing number of metallization levels and decreasing of power supply voltage, the debug and failure analysis of advanced CMOS designs requires the implementation of specific backside sample preparation methodologies and backside measurement flow.This paper describes the diagnosis and backside failure analysis flow implemented to successfully debug a flip-flop cell designed in 65 nm CMOS technology.     

Time gating imaging through thick silicon substrate: a new step towards backside characterisation

We propose in this paper a new backside imaging technique. Due to the constant increase ofnumerous metal layers, active areas can no longer be characterized through the frontside component. Nowadays, the most advanced imaging and failure analysis techniques require a modified backside component to allow probing. We propose a technique, where sample preparations are minimized. An optical time gating is used to reduce artefacts coming from the backside surface.     

High-Brightness InGaN–GaN Power Flip-Chip LEDs

We report the fabrication of InGaN–GaN power flip-chip (FC) light-emitting diodes (LEDs) with a roughened sapphire backside surface prepared by grinding. It was found that we can increase output power of the FC LED by about 35% by roughening the backside surface of the sapphire substrate. The reliability of the proposed device was also better, as compared to power FC LEDs with a conventional flat sapphire backside surface.      

Failure analysis of die-attachment on static random access memory (SRAM) semiconductor devices

Different combinations of the SRAM die and the substrates to yield a better die-attachment are studied. Cleanliness of die backside, plasma etching of contaminated die backside, new frames and old frames are the factors considered. The number of rejects due to die cracking in the die-attachment can be minimized if (1) production die and new frames are used, (2) 100% eutectic coverage is performed, (3) no gold preforms is added for substrates that are already coated with a thin layer of 98% Au-2% Si and (4) plasma etcher is used in clean surface preparation for suspected contaminated die backside surfaces. To whom correspondence should be adressed.     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed     

A review of sample backside preparation techniques for VLSI

A review of backside sample preparation techniques is presented. These techniques cover mechanical, chemical and other novel approaches such as laser ablation for ceramic and plastic package opening, silicon thinning and silicon polishing. To illustrate the milling process, we present two challenging backside sample preparation examples on a ceramic package and on a TSOP package.     

用单片清洗设备进行晶圆背面清洗

晶圆背面的污染降低了半导体器件的成品率,而当器件进入100nm技术节点之后成品率的降低便显得尤为重要。因此,目前众多的器件制造厂家就要求在进行片子正面清洗的同时对其背面也能够实现清洗。由Akrion公司制造的Mach2HP系统就是这样一种单片清洗设备,它具有清洗晶圆正反两面的功能。在起初评价时,设备经过了大量的粒子去除效率的变化。这种大量的变化使我们不能了解这种设备真实的清洗能力。氮化硅(Si3N4)粒子污染的晶片被用以进行粒子去除效率测试。我们发现有Si3N4粒子的晶片引起了背面粒子去除效率的变化。这种含Si3N4粒子的晶片是通过在裸芯片上沉积Si3N4粒子而特意准备的。我们发现,一些较大的Si3N4粒子在晶片清洗时又分解成更小的粒子。如若在清洗之后分解的粒子仍保留在晶片上,它们便会降低晶片总的粒子去除效果。因此,在这些粒子沉积到晶片上之前,这些粒子群需要进一步分解成实际的粒子。经过了解晶片的预习处理,我们实现了这种清洗设备背面清洗效果的评价。     

Wafer level backside emission microscopy: sample preparation

Emission microscopy has been widely adopted as an important tool for analyzing integrated circuit failures from the front surface. More recently, the development of multi-level metallization, flip-chip and lead-on-chip package designs either eliminated or greatly restricted this inspection avenue. An obvious alternative is to inspect from the backside of semiconductors. However, as silicon itself is a light-blocking material, thinning the back surface becomes essential to successful backside emission microscopy (EM). This paper describes a thinning and polishing technique enabling a user to locally thin a defective die on a wafer. This local thinning and polishing allows the wafer to retain its overall mechanical strength to survive the subsequent microprobing while providing a viewing window for EM analysis through the backside.     

SiC晶圆背面激光退火工艺研究

降低芯片背面金属-半导体欧姆接触电阻是有效提高器件性能的方式之一。采用650 V SiC肖特基势垒二极管(SBD)工艺,使用波长355 nm不同能量的脉冲激光进行退火实验,利用X射线衍射(XRD)和探针台对晶圆背面镍硅合金进行测量分析,得出最佳能量为3.6 J/cm²。退火后采用扫描电子显微镜(SEM)观察晶圆背面碳团簇,针对背面的碳团簇问题,在Ar;气氛下对晶圆进行了表面处理,使用SEM和探针台分别对两组样品的表面形貌和电压-电流特性进行了对比分析。实验结果表明,通过表面处理可以有效降低表面的碳含量,并且使器件正向压降均值降低了6%,利用圆形传输线模型(CTLM)测得芯片的比导通电阻为9.7×10^-6Ω·cm²。器件性能和均匀性都得到提高。     

Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate

In this paper, we propose a method to design charge-sensing elements for CMOS image sensor pixels on a silicon-on-sapphire (SOS) substrate. To address the low quantum efficiency problem due to very thin active film used, a backside illuminated lateral PIN photodiode on an SOS substrate is proposed and developed. It has the advantages of higher photo response with a PIN structure and improved optical transmission with a backside illumination through a transparent sapphire substrate. An active pixel sensor (APS) based on the PIN and backside illumination has been implemented in a commercially available SOS CMOS process. Acceptable sensitivity in optical conversion from the APS can be achieved, even with the ultrathin silicon film. The APS is demonstrated to function at 1.2 V, giving a dynamic range of 51 dB.     

Regulating Top‐Surface Multilayer/Single‐Crystal Graphene Growth by “Gettering” Carbon Diffusion at Backside of the Copper Foil

A unique strategy is reported to constrain the nucleation centers for multilayer graphene (MLG) and, later, single‐crystal graphene domains by gettering carbon source on backside of the flat Cu foil, during chemical vapor deposition. Hitherto, for a flat Cu foil, the top‐surface‐based growth mechanism is emphasized, while overlooking the graphene on the backside. However, the systematic experimental findings indicate a strong correlation between the backside graphene and the nucleation centers on the top‐surface, governed by the carbon diffusion through the bulk Cu. This understanding steers to devise a strategy to mitigate the carbon diffusion to the top‐surface by using a carbon “getter” substrate, such as nickel, on the backside of the Cu foil. Depth profiling of the nickel substrate, along with the density functional theory calculations, verifies the gettering role of the nickel support. The implementation of the backside carbon gettering approach on single‐crystal graphene growth results in lowering the nucleation density by two orders of magnitude. This enables the single‐crystal domains to grow by 6 mm laterally on the untreated Cu foil. Finally, the growth of large‐area polycrystalline single layer graphene, free of unwanted MLG domains, with significantly improved field‐effect mobility of ≈6800 cm² V^?1 s^?1 is demonstrated.     

利用分光光度计测量光学晶体的折射率

晶体折射率的准确测定是晶体上薄膜器件设计的基础。介绍了利用分光光度计测量晶体折射率的方法，通过背面影响系数法、背面镀增透膜和将两者结合起来的方法消除晶体反射率测量时背面反射带来的影响，给出了具体的步骤并对测量误差进行了分析。由于晶体的光学各向异性，采用起偏器扫描的方法测量晶体光学性质随方向的变化。通过对LiB3P5晶体的折射率的测量，证实了该方法的可行性并可用于其他光学晶体折射率的测量。     

（论坛）采用ALD方法制备TiO2/Al2O3布拉格反射镜并配合金属反射镜来增强背镀结构的反射效率

文中首次采用原子层沉积法制备TiO2/Al2O3布拉格反射镜并配合金属反射镜来制备了高反射率的背反射镜。制备的多层布拉格反射镜加Al镜和多层布拉格反射镜加Ag镜有很好的平整度和厚度的精确性,并且反射率高于96%。此外,TiO2/Al2O3布拉格反射镜和Al与蓝宝石衬底都有良好的粘合性,这样可以节省制备步骤并且可以得到高质量的背反射镜。利用原子层沉积技术和TiO2/Al2O3布拉格反射镜,我们得到了高反射率,角度依赖性小,更加稳定以及均一性更好的背反射镜,可以满足高亮度LED的需求。     

一种实用的磷化铟MMIC背面工艺技术

采用湿法技术发展了磷化铟MMIC的背面通孔刻蚀工艺,PMMA用作粘片剂,InP衬底粘附于玻璃版上,溅射钽膜用作湿法刻蚀掩膜,HCl+H3PO4腐蚀液实现100μm的通孔腐蚀.已证实这种湿法通孔工艺宽容度大,精确可控.     

Backside failure analysis case study: Implementation of innovative Local Backside Deprocessing technique

This paper describes a failure analysis case study where innovative Local Backside Physical characterization technique was performed on an automotive custom Mix-Mode device.The full analysis flow is presented, starting with backside sample preparation in order to perform a backside electrical localization of the defect. Then the multiple challenges of that approach were discussed. The continuous need of decreasing the analysis cycle time was addressed without affecting the success ratio of such analysis flow. The part mechanical degradation was avoided with a local removal of the Silicon. That highly localized technique granted a direct access to the fault site.The tools and process used for this case are fully described underlining the main advantages of this technique in comparison to the global backside deprocessing or to other characterization techniques.That successful development was achieved while determining the failure mechanism, in correlation with the failure mode of the qualification reject.