Avalanche breakdown characteristics of a diffused P-N junction

A one-dimensional analysis is presented on the avalanche breakdown characteristics of a diffused p-n junction diode. By numerically integrating the carrier ionization rate in a junction space-charge layer, avalanche breakdown voltage is calculated for diffused diodes of silicon and germanium; this voltage is graphically illustrated throughout a range of parameters applicable to most practical situations. In addition, for calculating the maximum cutoff frequency of varactor diodes, junction capacity is similarly illustrated assuming the device is biased to avalanche breakdown. From these illustrations, and from an accompanying nomograph which relates the physical constants of a junction to its impurity atom gradient, the above parameters can be readily established without additional calculations. Further, examples are also presented to demonstrate the reduction of breakdown voltage resulting from a rapid increase of conductivity within the space-charge layer of a diffused p-n junction; this situation approximates many epitaxial and double diffused structures.     

Steady-state characteristics of three terminal inversion-controlled switches

The direct current-voltage (I–V) characteristics of three terminal inversion controlled switches are described. These devices are layered sequences of metal/conducting “insulator”/semiconductor junction with electrical terminals at the metal and both sides of the junction. If a bias is applied between the metal and the far side of the junction, in the sense which tends to deplete the surface and forward bias the junction, the device shows bistable impedance states similar to the current-voltage characteristics of a silicon-controlled rectifier. The intermediate terminal which contacts the semiconductor region between the insulator and the junction, can be used, in proper circuit and biasing arrangements, to switch the device both into and out of its low impedance state without varying the voltage supplied to the outer terminals of the device and a series-connected resistor. The I–V characteristics of these three terminal devices support the inversion-controlled conduction model of device behavior which permits high conductivity of the device only when inversion of the semi-conductor surface occurs. The high and low impedance states and the pulses required to induce transistions between states are contained entirely within the “active” bias configuration for these devices, which is defined by analogy with the active bias region of conventional bipolar transistors.     

A high-voltage light-activated thyristor with a novel over-voltageself-protection structure

A high-voltage self-protected thyristor with a well structure formed in its p-base layer whose operation is based on avalanche breakdown is described. The device structure is simple and easy to fabricate compared to other avalanche-type devices. Numerical analyses and experiments demonstrate that the breakover voltage can be controlled by varying the well diameter and/or its depth. The breakdown voltage fluctuation of the device is 10% when the junction temperature is varied from 23 to 100°C. The device is turned on safely at 7300 V     

Photoinduced Contact Evolution and Junction Rearrangement in Two-Dimensional van der Waals Heterostructure

Devices based on 2DMs van der Waals (vdW) heterostructures always compose of multiple contacts. Due to the instability of nanoscale 2DMs and interfaces, these contacts can be affected by the operation-induced photo or thermal effect. They can trigger the evolution of junctions and rearrange the junctions across a device, which are detrimental for applications. Herein, vdW heterostructure of indium selenide (InSe) and black phosphorus (BP) on Au electrodes are investigated to reveal the contact evolution and its relation to device performance. During operation, light irradiation changes the I–V characteristics from symmetry to strong rectification. Photocurrent mapping and Kelvin-probe force microscopy (KPFM) reveal triple junctions in this heterostructure, i.e., Au-InSe junction, InSe homojunction, and InSe-BP heterojunction. The variation of I–V characteristics of vdW heterostructure is ascribed to the evolution of Au-InSe junction from quasi-ohmic junction with a near-zero work function difference (Δφ) to a strong Schottky junction (Δφ = ≈0.27 eV). The stabilized device demonstrates distinguished time-domain response at individual junctions and overall device, indicating the evolution of contacts and the consequent opposite junction directions degrade the overall device performance. This research emphasizes the importance of dealing with heterogeneous contacts and junction directions in designing vdW heterostructure photodetectors.     

Multi-emitter Si/GexSi1-x heterojunctionbipolar transistor with no base contact and enhanced logic functionality

We demonstrate multi-emitter Si/Ge_xSi_1-x n-p-n heterojunction bipolar transistors (HBT's) which require no base contact for transistor operation. The base current is supplied by the additional emitter contact under reverse bias due to the heavy doping of the emitter-base junction. Large-area HBT test structures exhibit good transistor characteristics, with current gain β≈400 regardless of whether the base current is supplied by a test base electrode or one of the emitter contacts. These devices have enhanced logic functionality because of emitter contact symmetry. Since device fabrication does not require base electrode formation, the number of processing steps can be reduced without significant penalty to HBT performance     

Scaling the Si MOSFET: from bulk to SOI to bulk

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping     

A dynamic-threshold SOI device with a J-FET embedded sourcestructure and a merged body-bias-control transistor. I. A J-FET embeddedsource structure properties

The floating-body effects in SOI CMOSFETs are fully suppressed by embedding a J-FET source structure immediately beneath the source/drain junction. The drain of the J-FET consists of a Schottky barrier diode; the holes generated in the body can easily be ejected into the source through the forward-biasing of this diode. The source-drain breakdown voltage and drain-induced barrier-lowering characteristics of this device are the same as those of a bulk device. With this structure, the body potential syncrhronously couples to the gate bias in the dynamic mode without potential hysteresis when the body-to-source resistance is properly designed. The inverter-chain delay time should be 45% of that of a bulk device operating at 1 V without an excess load     

Methodology for bipolar process diagnosis and its application to advanced self-aligned bipolar transistors

A methodology for bipolar process diagnosis is developed to evaluate advanced shallow profile bipolar technologies. In this method, the emitter-base leakage current (IEBO) is used as an indicative parameter for the degree of the intrinsic and extrinsic base overlap. By plotting the emitter-base leakage current (IEBO) site-by-site against other device parameters, such as the emitter-collector punchthrough current (ICEO), the collector saturation current density (JCS), and the current gain β, the influence of processing conditions on the device characteristics can be disclosed. An advanced "double-poly" self-aligned bipolar technology is used as an example to demonstrate the application of this method. The effects of the extrinsic base drive-in and the polysilicon emitter junction depth on the device characteristics are studied.     

High-power operation of index-guided inverted channel substrate planar (ICSP) lasers

An easily fabricated high-power index-guided laser, the inverted channel substrate planar (ICSP) structure, has been developed using the two-step metal-organic chemical vapour deposition (MOCVD) technique. Linear output power characteristics were observed to 30 mW CW on submount with junction side up without facet coatings. The device operated in a stable single mode to a power >25 mW. Improved ICSP lasers with facet coatings demonstrate a stable high output power of 65 mW CW and a differential quantum efficiency of 60%.     

Symmetrical N-port waveguide junction loaded with dielectric sleeveand metallic post

The present paper describes the development of a computer model that is able to predict the characteristics of the symmetrical N-port waveguide junction, which has a dielectric sleeve and metallic post inserted concentrically into its central cavity. Computational and experimental test results demonstrate that the resultant software package (which is compact enough to be run on an IBM 486 PC) can yield accuracies of ±0.5% for the scattering parameters of the junction     

Computer-aided transistor design, characterization, and optimization

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors using major process parameters such as dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration is described. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.     

A new technique for determining the capacitive couplingcoefficients in flash EPROMs

A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures     

Influences of surface sulfur treatments on the temperature-dependent characteristics of HBTs

The temperature-dependent DC characteristics of InGaP-GaAs heterojunction bipolar transistors with and without sulfur treatment are systematically studied and demonstrated. Due to the use of sulfur passivation, the series resistance of base-emitter junction of studied device can be effectively reduced. In addition, the device with sulfur treatment can be operated under ultra low collector current regimes (I/sub C//spl les/10/sup -11/ A). Experimentally, a long-time sulfur treatment is not appropriate. In this work, the studied device with sulfur treatment for 15 min is a good choice. Furthermore, at measured temperature (298 K-398 K), the studied device with sulfur treatment can reduce collector-emitter offset voltage and the impact of emitter size effect. Moreover, as the temperature is increased, the device with sulfur treatment will exhibit higher DC current gain and more stable temperature-dependent performances. This will extend the application regimes of the studied device in low-power and communication systems.     

Modular bipolar analysis: Part I—Theory

A set of general recursive equations that are used with a generalized modular model is described. The model is used to analyze realistic bipolar junction devices from their physical geometries and impurity profiles. An individual device is partitioned into simple one-dimensional modules which enables the closed recursive equations to be used in solving for each module's electrical parameters. A companion paper describes how the individual module parameters are then superimposed upon the physical structure to obtain the intrinsic parameters that electrically represents the bipolar junction device. The device can be fully analyzed on any circuit analysis program by adding its appropriate bulk resistances and junction capacitances.     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

Employing vertical dielectric layers to improve the operation performance of flash memory devices

A number of new device structures have been reported recently to improve the operation performance of flash memory. In this work, a novel flash device with a vertical dielectric layer in the depletion region is proposed through simulation approach. The simulation results show that the employment of a vertical dielectric layer in the depletion region can improve the operation performance of flash memory. The improvement can be attributed to a lower potential in the central region of device channel and the increase of the potential drop in the channel direction near drain junction. Thus, this proposed vertical dielectric layer increases the electrical field of the channel and thus the probability and the momentum of electron injection. The operation characteristics of the flash device with a vertical dielectric layer in the depletion region of source and drain are superior to those without. In addition, it is found that a vertical dielectric layer with lower dielectric constant can enhance the operation performance of flash device even more.     

An integrated silicon magnetic field sensor using the magnetodiode principle

We report a novel integrated magnetic field sensitive device. Its structure is reminiscent of the bipolar transistor, but its operation is essentially that of a magnetodiode: a reverse-biased p-n (collector) junction plays a role similar to that of the high recombining surface of classical magnetodiodes. The device can be manufactured in standard bulk CMOS or bipolar technology. Sensitivity up to 25 V/T at 10-mA current is achieved. Voltage-current characteristics shows saturation and negative resistance regions, which are explained by JFET and UJT effects, respectively.     

根据行为级模型方法对CMOS 图像传感器的BJPG 晶体管的分析

本文提出一种新的用于CMOS图像传感器像素的光电检测器－－双极结型光栅晶体管。由于引入p^ n注入结，光电荷的读出速率大大增加，改善了CMOS图像传感器的工作速率和响应灵敏度。尽管传统的光电集成电路的电路级模拟采用微电子集成电路的模拟方法，但是光电子集成电路不仅含有微电子器件和电信号还含有光电检测器和光信号，采用传统的集成电路模拟方法有其局限性。本文提出一种行为级模拟方法（光电子检测器设计的新方法，利用C、MATLAB和HSPICE等语言写出光电子器件的模拟器）来模拟分析双极结型光栅晶体管的特性。基于0.6μm CMOS工艺的分析结果表明双极结型光栅晶体管在不同栅氧化层厚度随栅压变化与传统光栅晶体管的特性一样，但光电流密度呈指数式增长且光电流密度增大，因此改善了CMOS图像传感器的工作速率和响应灵敏度。     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage