W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.      

Single- and Dual-Polarized Tunable Slot-Ring Antennas

Single- and dual-polarized slot-ring antennas with wideband tuning using varactor diodes have been demonstrated. The single-polarized antenna tunes from 0.95 to 1.8 GHz with better than ${-}13$ dB return loss. Both polarizations of the dual-polarized antenna tune from 0.93 to 1.6 GHz independently with better than ${-}10$ dB return loss and $> !20!$ dB port-to-port isolation over most of the tuning range. The capacitance of the varactor diodes varies from 0.45 to 2.5 pF, and the antennas are printed on 70 $,times,$70 $,times,$0.787 mm ${^3}$ substrates with ${epsilon_{rm r} = 2.2}$. The dual-polarized slot-ring antenna can either be made both frequency- and polarization-agile simultaneously, or can operate at two independent frequencies on two orthogonal polarizations. To our knowledge, this is the first dual-polarized tunable antenna with independent control of both polarizations over a 1.7:1 frequency range.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.      

A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-$Q$ above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- $Q$ above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point $({rm IP}_{{-}1~{rm dB}})$ is ${- 9.5}~{rm dBm}$ and the input referred third-order intercept point $(P _{rm IIP3})$ is ${+ 2.25}~{rm dBm}$. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.      

Design of a Beam Switching/Steering Butler Matrix for Phased Array System

A compact broadband 8-way Butler matrix integrated with tunable phase shifters is proposed to provide full beam switching/steering capability. The newly designed multilayer stripline Butler matrix exhibits an average insertion loss of 1.1 dB with amplitude variation less than $pm$2.2 dB and an average phase imbalance of less than 20.7$^{circ}$ from 1.6 GHz to 2.8 GHz. The circuit size is only $160times 100 {rm mm}^{2}$, which corresponds to an 85% size reduction compared with a comparable conventional microstrip 8-way Butler matrix. The stripline tunable phase shifter is designed based on the asymmetric reflection-type configuration, where a Chebyshev matching network is utilized to convert the port impedance from 50 $Omega$ to 25 $Omega$ so that a phase tuning range in excess of 120$^{circ}$ can be obtained from 1.6 GHz to 2.8 GHz. To demonstrate the beam switching/steering functionality, the proposed tunable Butler matrix is applied to a 1 $times$ 8 antenna array system. The measured radiation patterns show that the beam can be fully steered within a spatial range of 108 $^{circ}$.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

A 2–40 GHz Active Balun Using 0.13 $mu{rm m}$ CMOS Process

A 2 to 40 GHz broadband active balun using 0.13 $mu{rm m}$ CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of ${0} pm{1}~{rm dB}$, with the amplitude imbalances below 0.5 dB and the phase differences of ${180} pm {10} ^{circ}$ from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm $times,$ 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.      

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

Improved Microwave Noise Performance by SiN Passivation in AlGaN/GaN HEMTs on Si

Effects of silicon nitride (SiN) surface passivation by plasma enhanced chemical vapor deposition (PECVD) on microwave noise characteristics of AlGaN/GaN HEMTs on high-resistivity silicon (HR-Si) substrate have been investigated. About 25% improvement in the minimum noise figure $(NF_{min})$ (0.52 dB, from 2.03 dB to 1.51 dB) and 10% in the associate gain $(G_{rm a})$ (1.0 dB, from 10.3 dB to 11.3 dB) were observed after passivation. The equivalent circuit parameters and noise source parameters (including channel noise coefficient $(P)$, gate noise coefficient $(R)$, and their correlation coefficient $(C)$ ) were extracted. $P$ , $R$ and $C$ all increased after passivation and the increase of C contributes to the decrease of the noise figure. It was found that the improved microwave small signal and noise performance is mainly due to the increase of the intrinsic transconductance $(g_{{rm m}0})$ and the decrease of the extrinsic source resistance $(R_{rm s})$.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high-performance microelectromechanical systems solenoid inductors and metal—insulator—metal (MIM) capacitors by using a post-CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of compact filters are designed and fabricated, with the layout size of the bandpass filter as 0.65 $,times,$0.67 ${rm mm}^{ 2}$ and that of the low-pass filter as 0.77$,{ times },$1.25 ${rm mm}^{ 2}$. From the measurement results, the fifth-order low-pass filter shows less than 1.06 dB insertion loss up to 5 GHz and ${-}{rm 1.5}~{rm dB}$ cutoff frequency at 5.3 GHz. The bandpass filter is a second-order coupled-resonator type, with measured 4.3 dB minimum insertion loss and better than 13 dB return loss in the pass band. Both simulation and shock testing results have shown that the filters are almost free of influence from environmental vibration and shock. From the measured results in various temperatures, the bandpass filters were found to show lower loss under low temperatures, while the passband shift is negligible in the various temperatures. Together with the fabricated filters, the developed micromachining technique has demonstrated the potential of on-chip integration and miniaturization of passive RF circuits.      

Surface Deposition of Ionic Contaminants on Silicon Wafers in a Cleanroom Environment

The adsorption and desorption behaviors of ionic micro-contaminants on the silicon wafers in a cleanroom environment were investigated in this study. The experimental measurements showed that the surface density of ionic contaminants was significantly affected by both the exposure time and the properties of contaminants. The rate parameters of a kinetic model for surface deposition were determined by numerical optimization of fitting the experimental data on surface and ambient concentrations of airborne molecular contaminants (AMCs). Subsequently, the time-dependent deposition velocity and sticking coefficient of ionic species were obtained. The results showed that ${rm F}^{-}$, ${rm Cl}^{-}$, ${rm NO}_{3}^{-}$, ${rm SO}_{4}^{2-}$, ${rm Na}^{+}$, ${rm NH}_{4}^{+}$, ${rm K}^{+}$, and ${rm Mg}^{2+}$ were the major ionic microcontamination species on the wafer surfaces, with the adsorption rate constant and the sticking coefficient of ${rm K}^{+}$ ion being larger than those of other ionic contaminants. After the determination of sticking coefficients, the allowable wafer exposure durations and the maximum ambient concentrations of ionic species were exemplified based on the guideline recommended by the International Technology Roadmap for Semiconductors (ITRS).      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.