光探测器TO封装的高频分析与改进

推导了封装前后探测器的散射参数的关系,提出了探测器封装网络高频影响的两种分析方法.一种方法是直接比较封装前后探测器的频响,另一种则是从待封装探测器的反射系数和封装网络散射参数计算获得.以TO封装探测器为例,对两种方法的有效性进行了验证.分析结果表明,封装网络中电容和电感的谐振效应具有补偿作用,通过改变封装中的这些参数,改进了TO封装探测器的频响.     

光强探测器件

光迅科技已经推出的光强探测器件系列包括TO封装探测器，同轴探测器和TAP-PIN，其中TAP-PIN可以直接应用于光传输系统，DWDM器件，OADM器件，EDFA及喇曼放大器中信号光或泵浦光的光强探测，同轴探测器可以和光耦合器构成光强监测模块；TO封装探测器则是上述二者的核心部件。     

空间耦合高速光电探测器的等效建模与实现

大面积高速光电探测器是空间相干光通信系统的核心接收器件之一.通过分析光电二极管载流子运动规律,建立了PIN光电二极管高频等效模型,同时根据微波S参数理论,建立了光电二极管TO封装等效电路模型.根据空间相干光通信空间耦合方式对探测器光敏面大面积、高带宽的需求,将其应用于5 Gbps空间相干探测体系中平衡光电探测器的整体封...     

电吸收调制器和DFB激光器集成器件的测量

提出了一种测量电吸收调制器和激光器集成器件芯片散射参数的新方法.根据电吸收调制器和封装寄生参数的等效电路模型,对测量的反射系数进行拟合,得到封装寄生参数和电吸收调制器的等效电路元件的参数值.通过分析发现测试封装寄生参数对电吸收调制器的测试结果有很大影响.去除了封装寄生参数的影响后,得到了调制器的反射和传输参数的真实频响特性.     

电吸收调制器和DFB激光器集成器件的测量

提出了一种测量电吸收调制器和激光器集成器件芯片散射参数的新方法.根据电吸收调制器和封装寄生参数的等效电路模型,对测量的反射系数进行拟合,得到封装寄生参数和电吸收调制器的等效电路元件的参数值.通过分析发现测试封装寄生参数对电吸收调制器的测试结果有很大影响.去除了封装寄生参数的影响后,得到了调制器的反射和传输参数的真实频响特性     

星用红外探测器封装技术及其应用

本文简要介绍星用红外探测器的一些封装形式,重点阐述了红外探测器杜瓦组件封装的一些关键技术.这些技术的研究和发展,对提高红外探测器杜瓦组件封装技术水平和推进红外探测器尤其是红外焦平面的应用是至关重要的.     

高可靠性PIV光电探测器底座封装技术

针对PIN探测器易损坏、焊接等场合使用不便之缺点,提出一种新型高可靠性的探测器底座封装技术。实测特性表明,应用这种封装不仅没有降低PIN探测器性能,反而大大加强了探测器应用的牢固性。     

数模混合高速集成电路封装基板协同设计与验证

介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法.合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标.封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输.封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径.     

HgCdTe焦平面红外探测器封装中的芯片粘接技术

针对HgCdTe焦平面红外探测器封装的特殊性,提出了芯片粘接胶的选用原则,影响粘接质量的主要因素,以及粘接工艺优化方法.提出了用于封装 HgCdTe MW 320×256探测器的低温胶X1,并对该胶做了一系列可靠性实验.实验证明,低温胶X1满足该探测器的封装要求.     

非真空制冷型红外探测器小型化封装技术

基于红外探测系统对小体积制冷型红外探测器的应用需求,提出了一种新型非真空制冷型红外探测器小型化封装技术.阐述了其结构和工艺设计要点,实现了组件封装并通过耦合J-T制冷器进行了相关性能测试.结果 表明,本文所述的设计方案可实现128×128元(15 m) InSb芯片封装,组件尺寸小于等于Φ20 mm×15 mm,重量约...     

Measurement and Explanation of DC/RF Power Loci of an Active Patch Antenna

A case study of an active transmitting patch antenna revealed a characteristic loop locus of DC power versus RF output power as drive frequency was varied, with an operational bandwidth substantially smaller than the impedance bandwidth of the radiator. An approximate simulation technique, based on separation of the output capacitance of the power transistor, yielded easily visualized plots of power dependence on internal load impedance, and a simple interpretation of the experimental results in terms of a near‐resonance condition between the output capacitance and output packaging inductance.     

A multifunctional test chip for microelectronic packaging and its application on RF property measurements

This paper develops a multifunctional test chip for property extractions on packaging design. Components on this test chip include the diodes as the temperature sensors; the polysilicon units as the heaters; the piezoresistors as the stress sensors; and the pads as well as the related metal connector designs for the electrical parameter extractions. To save the sensor numbers and the connecting wires, sensors on the test chip surface were put according to structure symmetry. Since each packaging design has its individual size, components on the test chip surface were laid based on assembly of small unit cells, so that flexible test chip size can be obtained to fit the requirements from different packaging dimensions. The inductance and capacitance for the packaging leads were also extracted under microwave frequency operations, and a testing fixture was built to cooperate the Quad Flat Package (QFP) samples with the RF-RLC meter. The availability of the new measurement system designs was demonstrated from the testing data.     

A 10 Gb/s hybrid-integrated receiver array module using a planarlightwave circuit (PLC) platform including a novel assembly regionstructure

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing     

Characterization of Parasitics in TO-Packaged High-Speed Laser Modules

An elaborate analysis of the parasitic network of high-speed through-hole packaging (TO)-type laser modules is presented using a small-signal equivalent circuit model. The intrinsic laser diode is obtained using the optical modulation technique, and is embedded into the model as a separate component. Three step-by-step measurements are made for determining the packaging parasitic network, including the test fixture, TO header, submount, bonding wire, and parasitics of the laser chip. A good agreement between simulated and measured results confirms the validation and accuracy of the characterization procedures. Furthermore, several key parasitic elements are found based on the simulation of the high-frequency responses of the packaged devices. It is expected that the 3-dB bandwidth of 12 GHz or more of the low-cost TO packaged laser module may be achieved using the proposed optimization method     

一体化固态T/R组件前级电源设计

本文对基于隔离ZCS-Sepic-PFC变换器构成的一体化固态T/R组件前级电源的设计进行了描述。该变换器开关利用电感和电容谐振实现了零电流开关(ZCS),在高频化的同时降低了开关损耗,同时该变换器具有功率因数校正(PFC)的特性,适合应用于ac/dc电源中。文中对电路工作原理和功率因数校正的特性进行了详细分析,并给出组件前级电源的参数设计及电源部分工作波形。     

Nonlinearity of p-i-n photodetectors

At higher operating frequencies, the field dependence of the carrier velocity in p-i-n photodetectors generates harmonics and intermodulation products that can degrade the dynamic range of RF fiber-optic links. The authors present both a perturbational theory and measured harmonic data for a p-i-n photodiode operated at very high power densities which show that this and other detector nonlinear effects need not seriously compromise link performance. In particular, neither transit-time nor static nonlinearities in p-i-n photodiodes need limit the dynamic range of fiber-optic links operating below 5 GHz. The fact that the theoretical bandwidth of the photodiode, with all parasitic capacitance and inductance ideally removed, is 17 GHz, suggests that comparable spur-free performance should be achievable at X and Ku-band frequencies, once packaging parasitics are reduced     

无隔模带磁控管谐振系统的理论分析与仿真

为了提高磁控管稳定性,需要研究各耦合因素对磁控管谐振频率及模式分隔度的影响。该文采用等效电路的方法,给出了无隔模带磁控管在电容、电感耦合下的谐振频率及模式分隔度的表达式,并分析谐振频率随模数的变化趋势及电感、电容耦合强弱对模式分隔度的影响。采用CST-MWS软件对不同阴极半径及顶盖高度的谐振系统的谐振频率进行仿真,并将仿真结果与理论结果进行对比。理论分析与计算机仿真表明,对于无隔模带磁控管谐振系统,电容耦合使谐振频率随模数的增大而增大,电感耦合使谐振频率随模数的增大而减小;两者分别通过增大和降低模频率从而增大模式分隔度,两者共同作用时模谱图取决于占主导地位的耦合因素。     

High-speed Si-bipolar IC design for multi-Gb/s optical receivers

The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when V_ee is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose f_T was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.