共查询到19条相似文献,搜索用时 162 毫秒
1.
2.
3.
4.
5.
6.
本文简要介绍星用红外探测器的一些封装形式,重点阐述了红外探测器杜瓦组件封装的一些关键技术.这些技术的研究和发展,对提高红外探测器杜瓦组件封装技术水平和推进红外探测器尤其是红外焦平面的应用是至关重要的. 相似文献
7.
8.
介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法.合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标.封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输.封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径. 相似文献
9.
10.
11.
Neil J. McEwan Nazar T. Ali Kahtan A. Mezher Elmahdi A. El‐Khazmi Raed A. Abd‐Alhameed 《ETRI Journal》2011,33(1):6-12
A case study of an active transmitting patch antenna revealed a characteristic loop locus of DC power versus RF output power as drive frequency was varied, with an operational bandwidth substantially smaller than the impedance bandwidth of the radiator. An approximate simulation technique, based on separation of the output capacitance of the power transistor, yielded easily visualized plots of power dependence on internal load impedance, and a simple interpretation of the experimental results in terms of a near‐resonance condition between the output capacitance and output packaging inductance. 相似文献
12.
This paper develops a multifunctional test chip for property extractions on packaging design. Components on this test chip include the diodes as the temperature sensors; the polysilicon units as the heaters; the piezoresistors as the stress sensors; and the pads as well as the related metal connector designs for the electrical parameter extractions. To save the sensor numbers and the connecting wires, sensors on the test chip surface were put according to structure symmetry. Since each packaging design has its individual size, components on the test chip surface were laid based on assembly of small unit cells, so that flexible test chip size can be obtained to fit the requirements from different packaging dimensions. The inductance and capacitance for the packaging leads were also extracted under microwave frequency operations, and a testing fixture was built to cooperate the Quad Flat Package (QFP) samples with the RF-RLC meter. The availability of the new measurement system designs was demonstrated from the testing data. 相似文献
13.
Mino S. Ohyama T. Akahori Y. Hashimoto T. Yamada Y. Yanagisawa M. Muramoto Y. 《Lightwave Technology, Journal of》1996,14(11):2475-2482
A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing 相似文献
14.
An elaborate analysis of the parasitic network of high-speed through-hole packaging (TO)-type laser modules is presented using a small-signal equivalent circuit model. The intrinsic laser diode is obtained using the optical modulation technique, and is embedded into the model as a separate component. Three step-by-step measurements are made for determining the packaging parasitic network, including the test fixture, TO header, submount, bonding wire, and parasitics of the laser chip. A good agreement between simulated and measured results confirms the validation and accuracy of the characterization procedures. Furthermore, several key parasitic elements are found based on the simulation of the high-frequency responses of the packaged devices. It is expected that the 3-dB bandwidth of 12 GHz or more of the low-cost TO packaged laser module may be achieved using the proposed optimization method 相似文献
15.
本文对基于隔离ZCS-Sepic-PFC变换器构成的一体化固态T/R组件前级电源的设计进行了描述。该变换器开关利用电感和电容谐振实现了零电流开关(ZCS),在高频化的同时降低了开关损耗,同时该变换器具有功率因数校正(PFC)的特性,适合应用于ac/dc电源中。文中对电路工作原理和功率因数校正的特性进行了详细分析,并给出组件前级电源的参数设计及电源部分工作波形。 相似文献
16.
At higher operating frequencies, the field dependence of the carrier velocity in p-i-n photodetectors generates harmonics and intermodulation products that can degrade the dynamic range of RF fiber-optic links. The authors present both a perturbational theory and measured harmonic data for a p-i-n photodiode operated at very high power densities which show that this and other detector nonlinear effects need not seriously compromise link performance. In particular, neither transit-time nor static nonlinearities in p-i-n photodiodes need limit the dynamic range of fiber-optic links operating below 5 GHz. The fact that the theoretical bandwidth of the photodiode, with all parasitic capacitance and inductance ideally removed, is 17 GHz, suggests that comparable spur-free performance should be achievable at X and Ku -band frequencies, once packaging parasitics are reduced 相似文献
17.
为了提高磁控管稳定性,需要研究各耦合因素对磁控管谐振频率及模式分隔度的影响。该文采用等效电路的方法,给出了无隔模带磁控管在电容、电感耦合下的谐振频率及模式分隔度的表达式,并分析谐振频率随模数的变化趋势及电感、电容耦合强弱对模式分隔度的影响。采用CST-MWS软件对不同阴极半径及顶盖高度的谐振系统的谐振频率进行仿真,并将仿真结果与理论结果进行对比。理论分析与计算机仿真表明,对于无隔模带磁控管谐振系统,电容耦合使谐振频率随模数的增大而增大,电感耦合使谐振频率随模数的增大而减小;两者分别通过增大和降低模频率从而增大模式分隔度,两者共同作用时模谱图取决于占主导地位的耦合因素。 相似文献
18.
Hamano H. Yamamoto T. Nishizawa Y. Tahara A. Miyoshi H. Suzuki K. Nishimura A. 《Selected Areas in Communications, IEEE Journal on》1991,9(5):645-651
The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when V ee is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose f T was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s 相似文献
19.
A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp. 相似文献