深亚微米SoC芯片物理设计中基于串扰的时序收敛方法

当芯片设计进入深亚微米，串扰效应引起大量的设计违规，尤其是对时序收敛产生很大的影响。实际上串扰对电路时序性能的影响非常难估计，它不仅取决于电路互联拓扑，而且还取决于连线上信号的动态特征。文章从串扰延时的产生原因开始分析，并提出了在O．18μm及以下工艺条件下对串扰延时进行预防．分析和修复的时序收敛方法。     

片上网络中降低信号串扰的方法

NOC（片上网络）的体系结构解决了SOC（片上系统）在大规模集成IP核时面临的一些难题,但其串扰问题对电路性能的影响也越来越明显。基于DSM（深亚微米）下的总线模型,分析了信号串扰引起的总线延时问题,同时比较了3种减小总线串扰的编码方案。并采用0．13μmCMOS工艺对性能较优的DAP编码方案进行了电路仿真,得到了不同长度和宽度下的总线延时。结果表明,采用减少信号串扰的编码方法可以有效地降低总线的串扰,减少信号延时,这一效果当总线较宽或走线较长时尤其明显,同时也证明了0．13μmCMOS工艺下电路仿真结果与理论计算结果的一致性。     

作波分复用AWG同频串扰的相关特性及理论研究

本文讨论了光信号在阵列波导光栅（AWG）中同频光电流串扰的自相关函数,从理论上探讨了同频串扰的自相关系数,研究了相关系数与同频串扰引起延时的关系,及同频串扰噪声功率和串扰的极化方向的关系,得到了相关系数R_F与AWG延时时间τ、记录值n之间的关系曲线.数值计算表明:串扰延时使AWG的传输信号存在负相关、弱相关、正相关,其串扰延时对记录长度的影响呈周期性变化.     

基于分组网络结构NoC的BIST串扰测试方法

针对大规模NoC芯片设计中BIST测试时间长和消耗面积大的问题,提出一种测试NoC内switch间互连线串扰的BIST方法。对于互连线工作在1 GHz以下的大规模NoC,电容耦合是影响串扰的主要因素。通过并行测试结构,同时对几条受害线进行测试,有效减小了测试时间和电路面积。从理论角度对所提方法的测试时间和功率损耗进行了分析,以3×3 mesh结构的NoC为例,验证了所提方案和理论分析的正确性。     

基于增强型延时感知CSE算法的AES S盒电路优化设计

针对高级加密标准（AES）S-盒优化,提出了一种增强型延时感知公共项消除（CSE）算法.该算法能够在不同延时约束条件下优化多常数乘法运算电路,并给出从最小延时到最小面积全范围的面积-延时设计折中.采用该算法优化了基于冗余有限域算术的S盒实现电路,确定了延时最优、面积最优的两种S盒构造.实例优化结果表明所提出算法的优化效率高、优化结果整体延时小.所设计的S盒电路基于65nm CMOS工艺库综合,结果表明,对比于已有文献中S盒复合域实现电路,所提出面积最优S盒电路的面积-延时积最小,比目前最小面积与最短延时的S盒组合逻辑分别减少了17.58%和19.74%.     

针对级联型ⅡR滤波器群延时的均衡优化技术

为了减小由非恒定群延时所引起的滤波器的输出信号失真,本文提出一种适用于级联型无限长脉冲响应数字滤波器的群延时均衡优化方法.通过在级联型ⅡR数字滤波器每一级的输出插入全通均衡器,减小群延时在通带范围内的变化,进而减小滤波器的输出信号失真.对于本文提出的群延时优化方法,当采用1阶和2阶均衡器进行电路优化时,在0~100Hz的通带范围内,分别将群延时的变化量减小了28.19%和49.93%.基于0.18μm CMOS标准单元库进行逻辑综合与版图设计,最终得到整个滤波电路IP核版图的面积为0.1747mm².相比于已有文献方法,本文方法在群延时优化上效果显著,电路实现上功耗和面积较小,非常适合片上系统应用.     

基于多策略离散粒子群算法的MPRM电路延时与面积优化

针对大规模混合极性Reed-Muller(Mixed Polarity Reed-Muller,MPRM)逻辑电路的延时与面积优化,提出一种基于多策略离散粒子群优化(Multi-Strategy Discrete Particle Swarm Optimization,MSDPSO)的极性搜索方法.在MSDPSO算法中,对粒子进行团队划分,每个团队既执行不同策略,又相互联系,并行完成探索与开发的双重任务.同时在进化过程中采用高斯调整来激活寻优能力较差的粒子.结合MSDPSO算法和列表极性转换技术,对大规模MPRM电路进行延时与面积极性搜索.最后对PLA格式的MCNC Benchmark电路进行算法性能测试,结果验证了MSDPSO算法的有效性.与离散粒子群优化(Discrete Particle Swarm Optimization,DPSO)算法的优化结果相比较,MSDPSO算法获取的电路延时平均缩短8.43%,面积平均节省38.36%.     

考虑串扰影响的时延测试

超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生．大大提高了算法的效率。实验表明，以该算法实现的系统可以在一个可接受的时间内。对一定规模的电路的串扰时延故障进行测试产生。     

超立方体法在SM4算法S盒中的应用

S盒是商用密码算法SM4中最耗时的一部分,因此构造高性能的S盒具有重要意义.为了显著减少SM4算法进行加解密运算的延时,我们引入了N维超立方体法构造S盒,在硬件电路的实现上,相比于传统S盒的查表法延时缩短6%,面积减少17%.此方法同时适用于其它对称加密算法中的S盒变换,具有可借鉴性.     

降低射频电路串扰噪声的布线方法

研究并解决了无障碍多层无网格射频电路的布线问题,主要包括三个部分:设计规则、串扰噪声限制和布线方法.首先通过设计规则计算连线参数,运用RLc模型估算串扰噪声,然后,按照需要连接的实节点个数进行归类并提出相应的布线算法.实验结果表明,该布线方法可有效地降低射频电路的串扰噪声.     

An Efficient Method to Synthesize Reversible Logic by Using Positive Davio Decision Diagrams

Reversible logic is a key technique for quantum computing leading to quantum communication and quantum computer. However, the bottleneck of low efficiency in the synthesis procedure limits applications of reversible logic and cannot obtain optimized reversible circuits. In this paper, an efficient method based on positive Davio expansion to synthesize reversible circuits is proposed, which generates a positive Davio decision diagram for a logic function and transfers diagram nodes to reversible circuits. A matching template is given to help nodes transformation. The experimental results prove that compared with other synthesis methods, the proposed method can obviously optimize quantum cost and keep very short execution time.     

具有低量子代价的快速可逆逻辑综合方法研究

可逆逻辑是最子计算、低功耗设计和纳米技术领域的关键技术。目前可逆逻辑电路的综合方法效率较低、未能达到区域优化,所以,这些方法仪通用于小璎电路的综合。该文提出了一种基于Davio分解式的综合方法,该方法将逻辑函数转换成对应的正Davio决策图,然后通过对每个图节点模版匹配,最终生成可逆逻辑电路。此方法综合速度快,便于优化,适用于大型电路的综合。     

一种可逆有限状态机的电路设计

不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.     

Symbolic Analysis of Nullor-Based Circuits with the Two-Graph Technique

Symbolic analysis is a powerful tool which accelerates the electronic design process by providing insight about the behavior of a circuit. Recently, the analysis and synthesis of electronic circuits with nullors have received considerable attention. This is due to the fact that nullors are very flexible and versatile active elements. Very efficient analysis methods, such as nodal analysis, Coates flow graphs, and two-graphs are proposed in the literature and are widely used. It has arguably been reported (because it does not generate vanishing terms in the symbolic network functions) that the last cited analysis method may be considered as the most promising. Actually, using the two-graph method, symbolic transfer functions can be calculated via either signal flow graphs and Mason’s formula, without any restriction on the type of the sources (dependent and independent), or the spanning tree enumeration method for RLC circuits with nullor equivalent circuits of independent voltage sources and all types of controlled sources. In this paper we propose a new method for symbolic analysis of circuits with nullors using the two-graph method in both versions, i.e. signal flow graphs and enumeration of spanning trees. This new method helps us to see distinctly the relationships between various circuit components (for the method using the signal flow graph) and enables us to calculate the symbolic network functions without the excess terms (for the method using the enumeration of spanning trees).     

A library-based synthesis methodology for reversible logic

Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible circuits have been proposed so far. In this paper, a library-based synthesis methodology for reversible circuits is proposed where a reversible specification is considered as a permutation comprising a set of cycles. To this end, a pre-synthesis optimization step is introduced to construct a reversible specification from an irreversible function. In addition, a cycle-based representation model is presented to be used as an intermediate format in the proposed synthesis methodology. The selected intermediate format serves as a focal point for all potential representation models.In order to synthesize a given function, a library containing seven building blocks is used where each building block is a cycle of length less than 6. To synthesize large cycles, we also propose a decomposition algorithm which produces all possible minimal and inequivalent factorizations for a given cycle of length greater than 5. All decompositions contain the maximum number of disjoint cycles. The generated decompositions are used in conjunction with a novel cycle assignment algorithm which is proposed based on the graph matching problem to select the best possible cycle pairs. Then, each pair is synthesized by using the available components of the library. The decomposition algorithm together with the cycle assignment method are considered as a binding method which selects a building block from the library for each cycle. Finally, a post-synthesis optimization step is introduced to optimize the synthesis results in terms of different costs.To analyze the proposed methodology, various experiments are performed. Our analyses on the available reversible benchmark functions reveal that the proposed library-based synthesis methodology can produce low-cost circuits in some cases compared with the current approaches. The proposed methodology always converges and it typically synthesizes a give function fast. No garbage line is used for even permutations.     

可逆逻辑表达式的识别和图示方法

可逆逻辑电路是仅包含可逆运算的新型电路,还可根除源于信息损失的能耗和发热,是研究与实现超低功耗集成电路、量子计算机及信息安全等的关键基础。文中针对可逆逻辑电路研究的需要,研究了通过识别可逆逻辑表达式提取可逆逻辑电路结构信息,并加以图形化显示的有效方法和可行算法,以便更形象、直观地表达可逆逻辑电路综合、优化的结果,进而为分析、理解和优化可逆逻辑电路提供方便。     

基于矩阵编码的量子可逆逻辑电路进化设计方法

 本文研究基于遗传算法的量子可逆逻辑电路综合技术,能实现可逆逻辑电路功能、量子门数、垃圾位数和量子代价的多目标优化设计.建立了量子可逆逻辑电路综合数学模型,采用了量子可逆逻辑电路矩阵编码方案,设计了量子可逆逻辑电路进化操作算子,给出了量子可逆逻辑电路多目标进化设计算法.以8位量子可逆乘法器为设计实例,实验结果证明了所提出的量子可逆逻辑电路多目标进化设计方法是正确有效的.     

电路并行拓扑分析

提出了电路的并行拓扑分析法。该方法将节点撕裂法引入拓扑分析,完成对电路的并行处理,实现计算机对较大规模电路的并行符号分析,拓宽了符号分析法的应用"瓶颈",提高了符号分析的速度与效率。     

A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion

Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters     

通用Toffoli可逆门的固定故障测试

可逆电路技术在低功耗芯片和量子通信中广泛使用。目前,大部分学者着重研究可逆电路的合成,对电路的故障测试却很少问津,但是可逆电路的测试在应用中却十分重要。文中构造了一种四输入通用Toffoli门（universal toffoli gate,UTG）用来检测电路故障,这个门可以实现所有基本的布尔逻辑。UTG门可以检测到所...