A novel fully differential biopotential amplifier with dc suppression

Fully differential amplifiers yield large differential gains and also high common mode rejection ratio (CMRR), provided they do not include any unmatched grounded component. In biopotential measurements, however, the admissible gain of amplification stages located before dc suppression is usually limited by electrode offset voltage, which can saturate amplifier outputs. The standard solution is to first convert the differential input voltage to a single-ended voltage and then implement any other required functions, such as dc suppression and dc level restoring. This approach, however, yields a limited CMRR and may result in a relatively large equivalent input noise. This paper describes a novel fully differential biopotential amplifier based on a fully differential dc-suppression circuit that does not rely on any matched passive components, yet provides large CMRR and fast recovery from dc level transients. The proposed solution is particularly convenient for low supply voltage systems. An example implementation, based on standard low-power op amps and a single 5-V power supply, accepts input offset voltages up to +/-500 mV, yields a CMRR of 102 dB at 50 Hz, and provides, in accordance with the AAMI EC38 standard, a reset behavior for recovering from overloads or artifacts.     

Interference-rejection characteristics of biopotential amplifiers: a comparative analysis

The circuit parameters contributing to power line interference in ground-referenced, two- and three-electrode biopotential amplifiers, both isolated and nonisolated, are reviewed. The effects of external interference on different amplifiers are compared by using the 'effective coupling impedance' concept. Next, an analysis of the effect of imbalanced input impedances is carried out. It is concluded that the interference in an isolated amplifier is not always lower than in a nonisolated one, and that it must be reduced by an adequate sharing between the CMRR (common mode rejection ratio) and the IMRR (isolation mode rejection ratio); that an increase in common mode input impedance always reduces interferences in three-electrode amplifiers but not in two-electrode amplifiers; and that in two-electrode amplifiers, not only is the matching of input op amps important, but also the tolerance of components in first-stage circuits.<>     

一种基于准浮栅技术的折叠差分结构及其应用

提出了一种基于准浮栅技术的新型折叠差分结构,其偏置电流源的电压降被折叠到输出电压摆幅中,且不受共模输入电压限制而达到较大范围,非常适于低压应用。基于此结构,实现了一种超低压运算放大器。仿真分析表明,该运算放大器能够实现轨到轨(rail-to-rail)的共模输入电压范围和输出电压摆幅,以及较高的共模抑制比。     

Constant-Gm rail-to-rail common-mode rangeinput stage with minimum CMRR degradation

The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-μm feature size are given     

AC coupled three op-amp biopotential amplifier with active DC suppression

A three op-amps instrumentation amplifier (I.A) with active dc suppression is presented. dc suppression is achieved by means of a controlled floating source at the input stage, to compensate electrode and op-amps offset voltages. This isolated floating source is built around an optical-isolated device using a general-purpose optocoupler, working as a photovoltaic generator. The proposed circuit has many interesting characteristics regarding simplicity and cost, while preserving common mode rejection ratio (CMRR) and high input impedance characteristics of the classic three op-amps I.A. As an example, a biopotential amplifier with a gain of 80 dB, a lower cutoff frequency of 0.1 Hz, and a dc input range of +/- 8 mV was built and tested. Using general-purpose op-amps, a CMRR of 105 was achieved without trimmings.     

Common-mode rejection limitations of differential amplifiers

The common-mode rejection ratio (CMRR) equations of the differential pair and differential cascade amplifiers are reformulated in terms of imbalances in the saturation current. Early voltage, and current gain parameters of the transport model of the bipolar transistor. The effect of source resistance on CMRR is included in the formulation. The CMRR of this class of amplifier is shown to be limited by the magnitude and imbalance of the open-circuit voltage gain of the active devices. Also, a design characteristic, common to a wider class of differential amplifiers, is shown to produce a lower bound on the attainable CMRR.     

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-μm CMOS process model under supply voltage of ±0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Ω for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.     

差分放大电路单端输入信号的射极耦合传输及等效变换

用电路分析的方法对差分放大电路单端输入信号的射极耦合传输及等效变换进行了深入研究,目的是探索单端输入差分放大电路中输入信号的作用过程。差分放大电路的单端输入信号,经差分管的发射极耦合传输,在输入回路可等效变换为差模输入信号、共模输入信号的叠加,且等效变换时与发射极电阻Re取值大小无关,Re取值大小反映了对共模输入信号的抑制程度。所述方法的创新点是给出了单端输入信号在输入回路作用下的物理过程,完善了单端输入信号的等效变换方法。     

DVCC-based very low-offset current-mode instrumentation amplifier

This paper presents an alternative implementation of a chopper-modulated current-mode instrumentation amplifier. The structure provides very low-offset voltage at the output due to chopper modulation and residual offset removal path. The residual offset removal path is based on low-pass filtering using grounded capacitances which provides compact design structure compared to various chopper-modulated instrumentation amplifier designs. Rail-to-rail input common-mode range is possible due to transmission gate-based input chopper switching scheme. The design is made using a 0.35-µm CMOS process with ±1.65 V supply voltage. The area of the amplifier is 234µm × 344 µm, including all the filtering elements. The proposed circuit with residual offset removal path provides less than 1 µV input referred offset voltage. The advantage of the proposed instrumentation amplifier is its large bandwidth, simple design scheme and compact area compared to chopper-modulated voltage mode amplifiers.     

High CMRR current-feedback operational amplifier

Despite excellent high frequency and high speed performance, current-feedback operational amplifiers (CFOAs) generally exhibit poor common-mode rejection properties, which limits their utility. In this paper the authors analyse the conventional (CFOA) in terms of common-mode rejection ratio (CMRR) performance, and, having identified the mechanism primarily responsible for the CMRR, they present a modified CFOA input stage circuit design by introducing a combination of a bootstrapping technique and folded cascode transistors. Simulation results of this new CFOA architecture indicate that the amplifier has significantly improved both CMRR and gain accuracy. Other key characteristics are also improved, with the notable exception of slew rate, which is reduced as a consequence of the new topology.     

Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.     

Current mode instrumentation amplifier with rail-to-rail input and output

This paper presents the results from an investigation on the implementation of Current Mode Instrumentation Amplifiers (CMIAs) with rail-to-rail operational amplifiers (op amp) with a gm control circuit. The objective of employing rail-to-rail op amps in the implementation of a CMIA is the improvement of the common-mode operation range. The enhancement of the input common mode range (ICMR) is obtained using op amps with a rail-to-rail input stage followed by a cascode-based output stage. A prototype of the CMIA was implemented in standard 0.6 μm XFAB CMOS technology. Test results showed that the CMIA common mode range was extended but with moderated CMRR. To minimize this issue the amplifier was re-designed and sent to fabrication. Simulations with the components variations included were performed and showed the enhancement of the CMRR can be expected.     

关于差分放大器的几点讨论

差分放大器在电子线路中有着广泛的应用,在模拟电子技术的教学中是重要内容之一。提出了差分放大器除了在直耦放大器中克服零点漂移外,其设置的目地是可以对2个输入端的差进行放大,同时对在非对称下情况如何减少失调电压及共模电压的范围做了详细的介绍,这些对于教学和电路设计及电路的合理应用却是非常重要的。     

单端输入差分放大电路输入信号的等效变换

本文对单端输入差分放大电路发射极耦合传输的分析方法进行了深入研究,利用电路分析的方法将单端输入信号等效变换成差模输入信号与共模输入信号的叠加。指出等效变换并不需要发射极电阻Re很大的条件,Re的取值大小只反映对共模输入信号的抑制程度。并把这种方法与输入信号用数学方法等效变换进行了对比,得出这两种输入信号的等效变换方法具有等效性的结论。并介绍了单端输入差分放大电路的教学处理方法。     

Unifying the concepts of offset voltage and common-mode rejection ratio [bipolar differential amplifiers]

A unified treatment of offset voltage and common-mode rejection ratio (CMRR) of bipolar differential amplifiers using large signal models is presented. The offset voltage expressions for the differential pair and 741 stages are first calculated in terms of transport model parameters. CMRR may then be calculated from these expressions. Two distinct mechanisms contributing to CMRR are identified.     

Two-electrode biopotential measurements: power line interference analysis

In this paper, an analysis of power line interference in two-electrode biopotential measurement amplifiers is presented. A model of the amplifier that includes its input stage and takes into account the effects of the common mode input impedance Z(C) is proposed. This approach is valid for high Z(C) values, and also for some recently proposed low-Z(C) strategies. It is shown that power line interference rejection becomes minimal for extreme Z(C) values (null or infinite), depending on the electrode-skin impedance's unbalance deltaZ(E). For low deltaZ(E) values, minimal interference is achieved by a low Z(C) strategy (Z(C) = 0), while for high deltaZ(E) values a very high Z(C) is required. A critical deltaZ(E) is defined to select the best choice, as a function of the amplifier's Common Mode Rejection Ratio (CMRR) and stray coupling capacitances. Conclusions are verified experimentally using a biopotential amplifier specially designed for this test.     

A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability

A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage     

A wide-band monolithic instrumentation amplifier [application of voltage-current convertor]

Describes a new voltage-to-current converter. This converter combines accuracy with differential signal handling and a high common-mode rejection ratio (CMRR). An application in an instrumentation amplifier consisting of two voltage-to-current converters in a balancing circuit shows the versatility of these units in analog circuit design. A remarkable point of the instrumentation amplifier is that the bandwidth (800 kHz) remains constant although the voltage gain varies from 1 to 10/SUP 4/.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

一种新型运放相位反转保护电路

在高噪声环境下,如何抑制相位反转现象的发生,是双极型和JFET型运放在电力电子、工业控制和汽车电子等领域应用中的一个重要问题.基于运算放大器电路相位反转现象的发生机理,针对现有抑制方法的不足,提出了一种新型的相位反转保护电路.该保护电路结构紧凑,仅需3个双极型器件,且当运放输入信号处于正常共模输入范围时,对运放的性能参数,如差模信号增益、建立时间和静态功耗等,没有不利的影响.理论分析与仿真结果表明,该保护电路不仅避免了运放电路相位反转的发生,而且有效地抑制了伴随相位反转的过流现象.