4×4 arrays of FET-SEED embedded control 2×1optoelectronic switching nodes with electrical fan-out

We describe a 4 by 4 array of embedded control two input, one output optoelectronic switching nodes based on the field effect transistor self electro-optic effect device (FET-SEED) technology. The arrays have electrical fan-out to remove the loss associated with optical fan-out in the system application. Extensive testing was done on several arrays at 156 Mb/s per channel with optical switching energies below 100 fJ, with the output driver limiting the maximum data rate to 400 Mb/s. Power dissipation, noise margin, crosstalk, sensitivity to stray light, and uniformity of both threshold and output waveforms are also discussed     

A prototype 3D optically interconnected neural network

We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4×4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 10⁴/cm² seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation     

Optoelectronic multichip module integration for chip level opticalinterconnects

We have integrated an 850-nm vertical-cavity surface-emitting laser (VCSEL), its driver, and a diffractive lenslet array onto a single substrate to produce an integrated optoelectronic multichip module for signal fan-out and distribution. The diffractive element performs optical fan-out of the output beam from the VCSEL into an array of focused spots at a plane 1, 416 μm from the surface of the VCSEL. This corresponds to 160 μm from the surface of the diffractive lens. System design, fabrication, integration, and experimental characterization is presented     

A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10^-12 and a power consumption of 3.5 W.     

A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication

The feasibility of a 40 Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. The optical channel impairments are studied. A complete DSP framework is developed to cancel out the optical channel impairments as well as analog circuit imperfections. To validate that the 40 Gb/s system can be implemented in CMOS, an integrated QAM-16 transceiver with a carrier frequency of 13.32 GHz was designed and fabricated in a 0.14$muhbox m$, 1.5 V CMOS technology. The test chip occupies 3.6$hbox mm^2$of area and consumes 340 mW of power. Measurement results for a transmission link consisting of the CMOS QAM-16 modulator/demodulator, a directly modulated laser (DML), a 30 km single mode fiber and a p-i-n photo-detector are reported.     

Polylithic Integration of Electrical and Optical Interconnect Technologies for Gigascale Fiber-to-the-Chip Communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

采用单级CMOS-SEED集成芯片的ATM光交换模块

提出了一种ATM光交换模块的系统结构.这种ATM交换模块采用了单级CMOS-SEED混合集成电路芯片及少量的光学元件,具有吞吐量大、稳定性高、封装调试容易等特点.对模块所采用的光电子混合集成芯片及系统的光学结构进行了描述.     

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

A CMOS burst-mode optical transmitter for 1.25-Gb/s ethernet PON applications

This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-/spl mu/m CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.     

A vertical-cavity surface-emitting laser appliqued to a 0.8-/spl mu/m NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-/spl mu/m CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

An 8b 250MS/s 0.13μm CMOS ADC using variable references for VGA-to-WUXGA scaler chips

This work proposes an 8b 250MS/s 0.13??m CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13??m CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1?dB at 250?MS/s, respectively. The ADC with an active die area of 0.72?mm² consumes 58.8?C62.4?mW depending on input modes at 250?MS/s and 1.2?V.     

Optically interconnected electronic chips: a tutorial and review ofthe technology

Optoelectronic interconnects between VLSI chips have been identified by the Semiconductor Industry Association (SIA) Roadmap as one of the few solutions to overcoming the communication bandwidth bottleneck between VLSI chips. Large-scale demonstrators based on optical interconnects, when fully operational, can exhibit today the same aggregate bandwidth as that foreseen by the Roadmap for the year 2007. Massive parallelism, low input/output driving energy over large distances, and synchronous processing of hundreds of optical information input channels mean that these prototypes can potentially provide on/off communication rates in the tera-pin-Hz region (i.e., a total capacity of one terabit/s). After discussing the limitations of electrical interconnects this paper reviews the means of integrating optoelectronic components with VLSI chips, suitable types of optoelectronic device and the three main approaches to constructing optical data links: fibre-ribbons, planar waveguides and free-space optics     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

Photonic A/D conversion using low-temperature-grown GaAs MSM switches integrated with Si-CMOS

By linking the unique capabilities of photonic devices with the signal processing power of electronics, photonically sampled analog-to-digital (A/D) conversion systems have demonstrated the potential for superior performance over all-electrical A/D conversion systems. We adopt a photonic A/D conversion scheme using low-temperature (LT)-grown GaAs metal-semiconductor-metal (MSM) photoconductive switches integrated with Si-CMOS A/D converters. The large bandwidth of the LT GaAs switches and the low timing jitter and short width of mode-locked laser pulses are combined to accurately sample input frequencies up to several tens of gigahertz. CMOS A/D converters perform back-end digitization, and time-interleaving is used to increase the total sampling rate of the system. In this paper, we outline the development of this system, from optimization of the LT GaAs material, speed and responsivity measurements of the switches, bandwidth and linearity characterization of the first-stage optoelectronic sample-and-hold, to integration of the switches with CMOS chips. As a final proof-of-principle demonstration, a two-channel system was fabricated with LT GaAs MSM switches flip-chip bonded to CMOS A/D converters. When operated at an aggregate sampling rate of 160 megasamples/s, the prototype system exhibits /spl sim/3.5 effective number of bits (ENOB) of resolution for input signals up to 40 GHz.     

256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate     

A 70-Mbit/s (RZ) 16×16 crosspoint switch for ternary-encodedsignals

An experimental 16×16 crosspoint switch that can switch ternary signals and handle data rates of up to 70 Mb/s return-to-zero (RZ) (equivalent to 140-Mb/s nonreturn-to-zero (NRZ)) per channel is described. Ternary signals, in particular, alternate mark inversion (AMI) encoded signals, are widely used in telephone interoffice digital-transmission systems. This chip could be used in an asynchronous cross-connection system at the DS3 (44.736-Mb/s) signal level. This crosspoint chip has 16 input and 16 output channels. Any input can be connected to any output or outputs without blocking. The architecture allows for paralleling many chips to increase the size of the crosspoint array and also for cascading them to provide multistage switching capability. The switch can be addressed in the same way as a memory chip, and the cross-connection map can be written to and read back from the device. The chip is fabricated using a standard 2-μm CMOS technology, and the die size is 20.16 mm² (177.2×176.4 mil), containing about 11000 transistors     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s