Assessment of high-frequency performance limits of graphene field-effect transistors

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20 nm have been examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is significant for sub-100 nm graphene FETs, it is possible to achieve a good transconductance and ballistic on-off ratio larger than 3 even at a channel length of 20 nm. At a channel length of 20 nm, the intrinsic cut-off frequency remains at a few THz for various gate insulator thickness values, but a thin gate insulator is necessary for a good transconductance and smaller degradation of cut-off frequency in the presence of parasitic capacitance. The intrinsic cut-off frequency is close to the LC characteristic frequency set by graphene kinetic inductance (L) and quantum capacitance (C), which is about 100 GHz·μm divided by the gate length.      

InAs/InP radial nanowire heterostructures as high electron mobility devices

Radial core/shell nanowires (NWs) represent an important class of one-dimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum-confined, high-mobility electron carriers. Transmission electron microscopy studies revealed single-crystal InAs cores with epitaxial InP shells 2-3 nm in thickness, and energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed heterostructure. Room-temperature electrical measurements on InAs/InP NW field-effect transistors (NWFETs) showed significant improvement in the on-current and transconductance compared to InAs NWFETs fabricated in parallel, with a room-temperature electron mobility, 11,500 cm(2)/Vs, substantially higher than other synthesized 1D nanostructures. In addition, NWFET devices configured with integral high dielectric constant gate oxide and top-gate structure yielded scaled on-currents up to 3.2 mA/microm, which are larger than values reported for other n-channel FETs. The design and realization of high electron mobility InAs/InP NWs extends our toolbox of nanoscale building blocks and opens up opportunities for fundamental and applied studies of quantum coherent transport and high-speed, low-power nanoelectronic circuits.     

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.     

Role of confinement on carrier transport in Ge-Si(x)Ge(1-x) core-shell nanowires

We examine the impact of shell content and the associated hole confinement on carrier transport in Ge-Si(x)Ge(1-x) core-shell nanowires (NWs). Using NWs with different Si(x)Ge(1-x) shell compositions (x = 0.5 and 0.7), we fabricate NW field-effect transistors (FETs) with highly doped source/drain and examine their characteristics dependence on shell content. The results demonstrate a 2-fold higher mobility at room temperature, and a 3-fold higher mobility at 77K in the NW FETs with higher (x = 0.7) Si shell content by comparison to those with lower (x = 0.5) Si shell content. Moreover, the carrier mobility shows a stronger temperature dependence in Ge-Si(x)Ge(1-x) core-shell NWs with high Si content, indicating a reduced charge impurity scattering. The results establish that carrier confinement plays a key role in realizing high mobility core-shell NW FETs.     

Surface channel MESFETs on hydrogenated diamond

Metal–semiconductor field effect transistors (MESFETs) based on hydrogen terminated diamond were fabricated according to different layouts. Aluminum gates were used on single crystal and low-roughness polycrystalline diamond substrates while gold was used for ohmic contacts. Hydrogen terminated layers were deeply investigated by means of Hall bars and transfer length structures. Room temperature Hall and field effect mobility values in excess of 100 cm2 V?1 s?1 were measured on commercial and single crystal epitaxial growth (100) plates by using the same hydrogenation process. Hydrogen induced two-dimensional hole gas resulted in sheet resistances essentially stable and repeatable depending on the substrate quality. Self-aligned 400 nm gate length FETs on single crystal substrates showed current density and transconductance values>100 mA mm?1 and >40 mS mm?1, respectively. Devices with gate length LG=200 nm showed fMax=26.4 GHz and fT=13.2 GHz whereas those fabricated on polycrystalline diamond, with the same gate geometry, exceeded fMax=23 GHz and fT=7 GHz. This work focused on the optimization of a self-aligned gate structure with respect to the fixed drain-to-source structure with which we observed higher frequency values; the new structure resulted in improvement of DC characteristics, better impedance matching and a reduction in the fMax/fT ratio.     

Quantum behavior of graphene transistors near the scaling limit

The superior intrinsic properties of graphene have been a key research focus for the past few years. However, external components, such as metallic contacts, serve not only as essential probing elements, but also give rise to an effective electron cavity, which can form the basis for new quantum devices. In previous studies, quantum interference effects were demonstrated in graphene heterojunctions formed by a top gate. Here phase coherent transport behavior is demonstrated in a simple two terminal graphene structure with clearly resolved Fabry-Perot oscillations in sub-100 nm devices. By aggressively scaling the channel length down to 50 nm, we study the evolution of the graphene transistor from the channel-dominated diffusive regime to the contact-dominated ballistic regime. Key issues such as the current asymmetry, the question of Fermi level pinning by the contacts, the graphene screening determining the heterojunction barrier width, the scaling of minimum conductivity, and of the on/off current ratio are investigated.     

Electrical transport of bottom-up grown single-crystal Si(1-x)Ge(x) nanowire

In this work, we fabricated an Si(1-x)Ge(x) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) by using bottom-up grown single-crystal Si(1-x)Ge(x) NWs integrated with HfO(2) gate dielectric, TaN/Ta gate electrode and Pd Schottky source/drain electrodes, and investigated the electrical transport properties of Si(1-x)Ge(x) NWs. It is found that both undoped and phosphorus-doped Si(1-x)Ge(x) NW MOSFETs exhibit p-MOS operation while enhanced performance of higher I(on)～100?nA and I(on)/I(off)～10(5) are achieved from phosphorus-doped Si(1-x)Ge(x) NWs, which can be attributed to the reduction of the effective Schottky barrier height (SBH). Further improvement in gate control with a subthreshold slope of 142?mV?dec(-1) was obtained by reducing HfO(2) gate dielectric thickness. A comprehensive study on SBH between the Si(1-x)Ge(x) NW channel and Pd source/drain shows that a doped Si(1-x)Ge(x) NW has a lower effective SBH due to a thinner depletion width at the junction and the gate oxide thickness has negligible effect on effective SBH.     

Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics

We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW field-effect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.     

Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

Extrinsic resistance due to contacts and nonabrupt lateral extension doping profile can become a performance-limiter in ultrathin body double-gate FETs (DGFET). In this paper, two-dimensional device simulations are used to study and optimize the extrinsic resistance in a sub-20 nm gate length DGFET. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of nonabrupt doping on the short channel effects and series resistance. This optimization depends upon the maximum allowed off-state subthreshold leakage current and the electrostatic integrity of the device structure.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

Development of ultra-high density silicon nanowire arrays for electronics applications

This article reviews our recent progress on ultra-high density nanowires (NWs) array-based electronics. The superlattice nanowire pattern transfer (SNAP) method is utilized to produce aligned, ultra-high density Si NW arrays. We fi rst cover processing and materials issues related to achieving bulk-like conductivity characteristics from 10 20 nm wide Si NWs. We then discuss Si NW-based fi eld-effect transistors (FETs). These NWs & NW FETs provide terrifi c building blocks for various electronic circuits with applications to memory, energy conversion, fundamental physics, logic, and others. We focus our discussion on complementary symmetry NW logic circuitry, since that provides the most demanding metrics for guiding nanofabrication. Issues such as controlling the density and spatial distribution of both p-and n-type dopants within NW arrays are discussed, as are general methods for achieving Ohmic contacts to both p-and n-type NWs. These various materials and nanofabrication advances are brought together to demonstrate energy effi cient, complementary symmetry NW logic circuits.     

Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Germanium nanowires with 3-nm-diameter prepared by low temperature vapour-liquid-solid chemical vapour deposition

We report the growth of germanium nanowires (Ge NWs) with single-step temperature method via vapour-liquid-solid (VLS) mechanism in the low pressure chemical vapour deposition (CVD) reactor at 300 degrees C, 280 degrees C, and 260 degrees C. The catalyst used in our experiment was Au nanoparticles with equivalent thicknesses of 0.1 nm (average diameter approximately 3 nm), 0.3 nm (average diameter approximately 4 nm), 1 nm (average diameter approximately 6 nm), and 3 nm (average diameter approximately 14 nm). The Gibbs-Thomson effect was used to explain our experimental results. The Ge NWs grown at 300 degrees C tend to have tapered structure while the Ge NWs grown at 280 degrees C and 260 degrees C tend to have straight structure. Tapering was caused by the uncatalysed deposition of Ge atoms via CVD mechanism on the sidewalls of nanowire and significantly minimised at lower temperature. We observed that the growth at lower temperature yielded Ge NWs with smaller diameter and also observed that the diameter and length of Ge NWs increases with the size of Au nanoparticles for all growth temperatures. For the same size of Au nanoparticles, Ge NWs tend to be longer with a decrease in temperature. The Ge NWs grown at 260 degrees C from 0.1-nm-thick Au had diameter as small as approximately 3 nm, offering an opportunity to fabricate high-performance p-type ballistic Ge NW transistor, to realise nanowire solar cell with higher efficiency, and also to observe the quantum confinement effect.     

Comparison of the top-down and bottom-up approach to fabricate nanowire-based silicon/germanium heterostructures

Silicon nanowires (NWs) and vertical nanowire-based Si/Ge heterostructures are expected to be building blocks for future devices, e.g. field-effect transistors or thermoelectric elements. In principle two approaches can be applied to synthesise these NWs: the ‘bottom-up’ and the ‘top-down’ approach. The most common method for the former is the vapour-liquid-solid (VLS) mechanism which can also be applied to grow NWs by molecular beam epitaxy (MBE). Although MBE allows a precise growth control under highly reproducible conditions, the general nature of the growth process via a eutectic droplet prevents the synthesis of heterostructures with sharp interfaces and high Ge concentrations. We compare the VLS NW growth with two different top-down methods: The first is a combination of colloidal lithography and metal-assisted wet chemical etching, which is an inexpensive and fast method and results in large arrays of homogenous Si NWs with adjustable diameters down to 50 nm. The second top-down method combines the growth of Si/Ge superlattices by MBE with electron beam lithography and reactive ion etching. Again, large and homogeneous arrays of NWs were created, this time with a diameter of 40 nm and the Si/Ge superlattice inside.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Sub-10 nm self-enclosed self-limited nanofluidic channel arrays

We report a new method to fabricate self-enclosed optically transparent nanofluidic channel arrays with sub-10 nm channel width over large areas. Our method involves patterning nanoscale Si trenches using nanoimprint lithography (NIL), sealing the trenches into enclosed channels by ultrafast laser pulse melting and shrinking the channel sizes by self-limiting thermal oxidation. We demonstrate that 100 nm wide Si trenches can be sealed and shrunk to 9 nm wide and that lambda-phage DNA molecules can be effectively stretched by the channels.     

Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.     

Observation of hole accumulation in Ge/Si core/shell nanowires using off-axis electron holography

Hole accumulation in Ge/Si core/shell nanowires (NWs) has been observed and quantified using off-axis electron holography and other electron microscopy techniques. The epitaxial [110]-oriented Ge/Si core/shell NWs were grown on Si (111) substrates by chemical vapor deposition through the vapor-liquid-solid growth mechanism. High-angle annular-dark-field scanning transmission electron microscopy images and off-axis electron holograms were obtained from specific NWs. The excess phase shifts measured by electron holography across the NWs indicated the presence of holes inside the Ge cores. Calculations based on a simplified coaxial cylindrical model gave hole densities of (0.4 ± 0.2) /nm(3) in the core regions.     

High-performance carbon nanotube field effect transistors with a thin gate dielectric based on a self-assembled monolayer

Individual single-walled carbon nanotube (SWCNT) field effect transistors (FETs) with a 2 nm thick silane-based organic self-assembled monolayer (SAM) gate dielectric have been manufactured. The FETs exhibit a unique combination of excellent device performance parameters. In particular, they operate with a gate-source voltage of only -1 V and exhibit good saturation, large transconductance, and small hysteresis (相似文献   

MoS2 Negative‐Capacitance Field‐Effect Transistors with Subthreshold Swing below the Physics Limit

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec^‐1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the “Boltzmann tyranny”. Such MoS₂ negative‐capacitance field‐effect transistors (NC‐FETs) with self‐aligned top‐gated geometry demonstrated here pull down the SS value to 42.5 mV dec^‐1, and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10⁶ with channel length less than 100 nm. Furthermore, the inserted HfO₂ layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF‐TrFE) from fatigue with robust stability. Notably, the fabricated MoS₂ NC‐FETs are distinctly different from traditional MOSFETs. The on‐state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC‐FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low‐power transistors needed for many exciting long‐endurance portable consumer products.