Analyzing the performance of SMP memory allocators with iterative MapReduce applications

The standard memory allocators of shared memory systems (SMPs) often provide poor performance, because they do not sufficiently reflect the access latencies of deep NUMA architectures with their on-chip, off-chip, and off-blade communication. We analyze memory allocation strategies for data-intensive MapReduce applications on SMPs with up to 512 cores and 2 TB memory. We compare the efficiency of the MapReduce frameworks MR-Search and Phoenix++ and provide performance results on two benchmark applications, k-means and shortest-path search.     

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems

We investigate how transactional memory can be adapted for embedded systems. We consider energy consumption and complexity to be driving concerns in the design of these systems and therefore adapt simple hardware transactional memory (HTM) schemes in our architectural design. We propose several different cache structures and contention management schemes to support HTM and evaluate them in terms of energy, performance, and complexity. We find that ignoring energy considerations can lead to poor design choices, particularly for resource-constrained embedded platforms. We conclude that with the right balance of energy efficiency and simplicity, HTM will become an attractive choice for future embedded system designs.     

A survey of memory management techniques in virtualized systems

Virtualization technology allows multiple operating systems to share hardware resources of a computer system in an isolated manner. Traditionally, memory is shared by an operating system using segmentation and paging techniques. With virtualization, memory partitioning and management has several new challenges. For isolated and safe execution, hypervisors do not provide direct access to hardware resources. Lack of direct access to the memory management hardware like page tables disqualifies direct usage of virtual memory solutions used on native (non-virtualized) setups. Further, aspects of dual control of the memory resource (by the guest OS and the hypervisor) and lack of semantics regarding memory usage in virtual machines present additional challenges for memory management. This paper surveys different techniques of memory partitioning and management across multiple guest OSs in a virtualized environment.An important goal of virtualization is to increase the physical machine utilization in order to save costs. With varying application demand for memory and diverse memory management policies of the guest OSs, ensuring optimal usage of memory is non-trivial. In this survey, challenges of memory management in virtualized systems, different memory management techniques with their implications, and optimizations to increase memory utilization are discussed in detail.     

A customisable memory management framework for C++

Automatic garbage collection relieves programmers from the burden of managing memory themselves and several techniques have been developed that make garbage collection feasible in many situations, including real time applications or within traditional programming languages. However, optimal performance cannot always be achieved by a uniform general purpose solution. Sometimes an algorithm exhibits a predictable pattern of memory usage that could be better handled specifically, delaying as much as possible the intervention of the general purpose collector. This leads to the requirement for algorithm specific customisation of the collector strategies. We present a dynamic memory management framework which can be customised to the needs of an algorithm, while preserving the convenience of automatic collection in the normal case. The Customisable Memory Manager (CMM) organises memory in multiple heaps. Each heap is an instance of C++ class which abstracts and encapsulates a particular storage discipline. The default heap for collectable objects uses the technique of mostly copying garbage collection, providing good performance and memory compaction. Customisation of the collector is achieved exploiting object orientation by defining specialised versions of the collector methods for each heap class. The object-oriented interface to the collector enables coexistence and coordination among the various collectors as well as integration with traditional code unaware of garbage collection. The CMM is implemented in C++ without any special support in the language or the compiler. The techniques used in the CMM are general enough to be applicable also to other languages. The performance of the CMM is analysed and compared to other conservative collectors for C/C++ in various configurations. © 1998 John Wiley & Sons, Ltd.     

计算机实验室的管理与维护

本文从计算机机房的管理与维护方面阐述了如何科学的、有效的管理计算机机房,从而为学生学习计算机技术提供良好的学习环境。要保障计算机实践教学,提高教学质量,就必须搞好计算机实验室的管理与维护工作,机房管理与维护主要包括设备的管理和软件及数据的管理与维护。     

Efficient execution of speculative threads and transactions with hardware transactional memory

Thread-level speculation (TLS) was researched to automatically parallelize portions of serial programs for execution, and transactional memory (TM) was studied as a promising alternative of lock for parallel programming due to its simplicity. Both TLS and TM require similar underlying support. In the paper, we present SeTM (sequential transactional memory), a hardware enhanced TM system which supports TLS at minor extra cost. Signature is an effective way to buffer speculative states in TM and TLS. But it cripples TM and TLS performance due to its false-positive in terms of conflict detection, especially for conflict-intensive TLS. SeTM adopts R/W bits and signature concurrently to ameliorate this bad influence. Additionally, SeTM introduces the fast rollback mechanism, which provides fast abort recovery for eager log-based HTM and TLS. The most important contribution of SeTM is the conflict-tolerant mechanism, which tolerates some ambiguous data conflicts in TLS. Finally, in order to achieve an efficient execution for these un-order transactions, we add an extra ordering mechanism for SeTM. With this ordering mechanism, the transactions in TM can also gain the performance improvement with the support of conflict-tolerant mechanism. Our evaluation major on TM and TLS separately. For the TLS applications, six representative benchmarks have been adopted to evaluate the above model. Our experimental results show that our scheme improves the execution performance of most tested codes at a modest hardware cost. For a set of important scientific loops, we report the highest speedup of 6.5 with 15 cores. Besides, experimental results also show good scalability of SeTM system. For the TM applications, with respect to LogTM-SE, the benchmarks from STAMP also gain performance improvement signally.     

Implicit ownership types for memory management

The Real-time Specification for Java (RTSJ) introduced a range of language features for explicit memory management. While the RTSJ gives programmers fine control over memory use and allows linear allocation and constant-time deallocation, the RTSJ relies upon dynamic runtime checks for safety, making it unsuitable for safety critical applications. We introduce ScopeJ, a statically-typed, multi-threaded, object calculus in which scopes are first class constructs. Scopes reify allocation contexts and provide a safe alternative to automatic memory management. Safety follows from the use of an ownership type system that enforces a topology on run-time patterns of references. ScopeJ’s type system is novel in that ownership annotations are implicit. This substantially reduces the burden for developers and increases the likelihood of adoption. The notion of implicit ownership is particularly appealing when combined with pluggable type systems, as one can apply different type constraints to different components of an application depending on the requirements without changing the source language. In related work we have demonstrated the usefulness of our approach in the context of highly-responsive systems and stream processing.     

Scoped types and aspects for real-time Java memory management

Real-time systems are notoriously difficult to design and implement, and, as many real-time problems are safety-critical, their solutions must be reliable as well as efficient and correct. While higher-level programming models (such as the Real-Time Specification for Java) permit real-time programmers to use language features that most programmers take for granted (objects, type checking, dynamic dispatch, and memory safety) the compromises required for real-time execution, especially concerning memory allocation, can create as many problems as they solve. This paper presents Scoped Types and Aspects for Real-Time Systems (STARS) a novel programming model for real-time systems. Scoped Types give programmers a clear model of their programs’ memory use, and, being statically checkable, prevent the run-time memory errors that bedevil the RTSJ. Adopting the integrated Scoped Types and Aspects approach can significantly improve both the quality and performance of a real-time Java systems, resulting in simpler systems that are reliable, efficient, and correct.

浅谈医院信息系统的维护和网络安全管理

随着信息技术的不管发展,医院网络化管理已经成为一种新的趋势。医院信息系统HIS的大规模使用,极大地提高了医务人员的工作效率,带来巨大的经济利益的同时,也为患者带来方便,节省了时间。HIS系统已经成为现代化医院运营必不可少的基础设施,如何构建一个科学、安全的HIS系统成为需要考虑的重要问题。本文从硬件和软件两个方面,分析了医院信息系统的维护和网络安全管理措施。     

存储器分级结构及其在微机中的应用

本文论述了存储器分级结构，即ｃａｃｈｅ—内存—外存三级结构的构成及作用，并说明了这种分级结构在微机中的应用现状。     

职业学校计算机机房管理与维护

随着教学信息化程度的提高,职业学校的机房建设发展很快,既是信息技术教学的重要组成部分和基本保证,也是校园网管理的重要组成部分。为了有效地管理好学校机房,提高机房的使用效率,延长机房设备的使用寿命,更好地服务教学工作,学校必须重视加强机房的管理与维护。本文就机房管理的问题,从机房的布置、硬件和软件三个方面作了探讨。     

基于冲突相关性检测的竞争管理模型

在无干扰特性下的软件事务存储系统中,竞争管理策略直接应用于冲突事务的消解,对具有整个系统的性能有直接的影响。针对现有竞争管理决策方式相对单一而产生的性能不稳定问题,提出了基于冲突相关性检测的竞争管理模型。该方法可以从过去的仲裁记录中分析冲突事务中存在的关联性,并把检测到的关联性作为当前冲突的决策依据,从而得到较优的冲突处理结果。在仿真平台采用该方法对部分基准数据结构的测试数据表明,该方法检测到并且帮助提交的冲突关联事务最多可占系统吞吐量的30%,其事务吞吐总量比其他参照对象的平均值高出约11%,具有较好的灵活度和适用性。     

Analyzing SLE 88 memory management security using Interacting State Machines

The Infineon SLE 88 is a smart card processor that offers strong protection mechanisms. One of them is a memory management system typically used for sandboxing application programs dynamically loaded on the chip. High-level (EAL5+) evaluation of the chip requires a formal security model.We formally model the memory management system as an Interacting State Machine and prove, using Isabelle/HOL, that the associated security requirements are met. We demonstrate that our approach enables an adequate level of abstraction, which results in an efficient analysis, and points out potential pitfalls like noninjective address translation.     

Optimal management of dynamic buffer caches

Optimal memory management strategies such as VMIN are generally considered unrealizable in view of the impracticality of obtaining a computation's reference string prior to execution. Addressing such strategies, this paper focuses on the dynamic management of variable-size buffer caches in the framework of the locality-set model, a memory management model that characterizes the reference behavior of a computation in terms of locality sets rather than reference strings. Several cost measures—the number of page faults, the space-time product, and one that combines them—are considered and conditions under which they are equivalent are derived. We define two novel strategies, PSETVMIN and SETVMIN, which manage buffer caches with and without prepaging, respectively, and prove that they minimize a cost measure that takes both page faults and the space-time product into account. The two strategies are of theoretical interest in view of their optimal behavior, but—more importantly—they are also realizable since only a limited amount of information about the reference behavior of a computation, the locality-set sequence, is required in advance. We demonstrate the use of these strategies for join processing in relational database management systems. The performance benefits of this technique are discussed and illustrated by simulation results.     

计算机硬件教学方法改革研究

介绍了计算机硬件教学的基本情况．提出了目前存在的一些问题。通过对结合网络教学、逆向思维、软硬件结合实验三方面的改革．取得了明昱的效果。最后总结了发展的趋势。     

Application execution management on the InteGrade opportunistic grid middleware

The InteGrade project is a multi-university effort to build a novel grid computing middleware based on the opportunistic use of resources belonging to user workstations. The InteGrade middleware currently enables the execution of sequential, bag-of-tasks, and parallel applications that follow the BSP or the MPI programming models.     

XP系统办公通信类附件工具的最少代码方案

本文介绍了如何用最少量的代码，自制XP系统办公通信类附件工具软件。     

The uniform memory hierarchy model of computation

TheUniform Memory Hierarchy (UMH) model introduced in this paper captures performance-relevant aspects of the hierarchical nature of computer memory. It is used to quantify architectural requirements of several algorithms and to ratify the faster speeds achieved by tuned implementations that use improved data-movement strategies.A sequential computer's memory is modeled as a sequence M ₀,M ₁,... of increasingly large memory modules. Computation takes place inM ₀. Thus,M ₀ might model a computer's central processor, whileM ₁ might be cache memory,M ₂ main memory, and so on. For each moduleM _u, a busB _u connects it with the next larger module M_u+1. All buses may be active simultaneously. Data is transferred along a bus in fixed-sized blocks. The size of these blocks, the time required to transfer a block, and the number of blocks that fit in a module are larger for modules farther from the processor. The UMH model is parametrized by the rate at which the blocksizes increase and by the ratio of the blockcount to the blocksize. A third parameter, the transfer-cost (inverse bandwidth) function, determines the time to transfer blocks at the different levels of the hierarchy.UMH analysis refines traditional methods of algorithm analysis by including the cost of data movement throughout the memory hierarchy. Thecommunication efficiency of a program is a ratio measuring the portion of UMH running time during which M₀ is active. An algorithm that can be implemented by a program whose communication efficiency is nonzero in the limit is said to becommunication- efficient. The communication efficiency of a program depends on the parameters of the UMH model, most importantly on the transfer-cost function. Athreshold function separates those transfer-cost functions for which an algorithm is communication-efficient from those that are too costly. Threshold functions for matrix transpose, standard matrix multiplication, and Fast Fourier Transform algorithms are established by exhibiting communication-efficient programs at the threshold and showing that more expensive transfer-cost functions are too costly.A parallel computer can be modeled as a tree of memory modules with computation occurring at the leaves. Threshold functions are established for multiplication ofN×N matrices using up to N² processors in a tree with constant branching factor.     

Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory

Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.     

自动化测试执行管理工具的研究与设计

主要设计并实现了一个自动化测试执行管理工具,并详细阐述了其总体框架、模块设计和关键技术的实现.该工具提供串行、并行、重复和分布式等多种测试执行顺序,可实时远程监控测试执行过程,并可提供详细的测试报告和多样的数据分析方法.