基于神经网络的片上互连线电感提取法

通过将具有自学习能力和记忆功能的神经网络应用于平行导体间的电感计算，结合移动窗口方法搜索作用域，实现片上互连寄生电感参数提取。仿真例子表明，此方法能够快速、有效地实现电感提取，可作为VLSI互连线性能分析、设计的有效向导。     

CMOS差分电感和串联电感对的建模与分析

该文分析了基于中芯国际0.18m CMOS工艺的差分电感和串联电感对,提出了电感在射频CMOS差分电路中的应用原则。研究了串联电感对之间的串扰效应,并提出了能准确反映互感效应、衬底容性损耗效应以及线圈间容性耦合的完整串扰模型。最后,通过对一组变间距的电感对进行测量分析,验证了该模型的准确性和适用性。     

RF集成电感的设计与寄生效应分析

分析了体硅 CMOS RF集成电路中电感的寄生效应 ,以及版图参数对电感品质因数 Q的影响 ,并通过Matlab程序模拟了在衬底电阻、金属条厚度、氧化层厚度改变时电感品质因数的变化 ,分析了不同应用频率时版图参数在寄生效应中所起的作用 ,得出了几条实用的设计原则并进行了实验验证 ,实验结果与模拟值符合得很好 ,表明此模拟方法与所得结论均可有效地用于指导射频 (RF)集成电路中集成电感的设计     

应用于无线收发机前端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下片上集成电感的设计和分析问题,包括片上螺旋型电感的有关版图、损耗机制、模型和参数提取问题,最后以一种被学术界广泛接受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原则.随着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛.     

射频电路中的电感

介绍了几种射频电路中常见的电感形式，给出了其电感值和Q值的计算公式．可用于工程中设计和分析电感．并阐述了几种电感的实际应用。     

高温超导耦合微带线动态电感模型

应用单根微带线内部电感计算的“增值电感规则”，提出一种计算高温超导耦合微带线动态电感的方法，即从无限簿的奇、偶模特性阻抗出发，求出无限薄耦合微带线的外部奇、偶模电感，经修正后得到有限厚的外部电感公式，再利用增值的电感规则及不同厚度时电感增值的不同特点，提出4种情况下电感增值的不同偏导形式，进而求出其相应的动态电感。该公式对超导电路元器件的设计和分析具有指导作用，其正确性通过两个计算实例得到了验证。     

应用于无线收发机关端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下集成电感的设计和分析问题,包括片上螺旋型电感的有关版图,损耗机制,模型和参数提取问题,最后以一种被学术界广泛妆受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原,有着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛。     

基于DC-DC转换器PFC电感的设计

本文主要是针对实际DC-DC应用电路,Boost升压电路中的PFC电感的设计进行了理论的分析和实验的验证。从设计的指标开始,如何推出电路中所需的电感值,给出了理论公式的推导,实验结果证明设计的PFC(功率因数校正)电感满足要求。     

砷化镓衬底上螺旋电感的建模和分析

针对砷化镓(GaAs)衬底上螺旋电感提出了一种改进形式的集总参数等效电路模型,该等效电路模型能很好地表征螺旋电感的高频效应.同时,应用电磁场全波分析方法对螺旋电感进行仿真,并分析各参数对电感性能的影响.从得到的散射参数中提取出有效电感、Q值和自谐振频率.基于参数优化方法提取等效电路模型中各元件值,并利用曲线拟合技术给出其相应的闭合表达式.这些表达式可用于射频和微波集成电路的设计,从而提高电路设计的性能和效率.     

低温共烧陶瓷埋置电感和电容的研究

讨论了低温共烧陶瓷(LTCC)埋置电感、电容的几何结构,并进行仿真,分析了结构变化对电感性能的影响,并进行实验制作,通过测试样品以验证仿真结果。仿真结果中找到的规律有效的节省了器件设计的时间,为等效模型的提取和元件库的建立奠定了一定的基础。     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-$mu$m CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.      

Gasping the impact of on-chip inductance

The rapid advancements in process technology and heightening market pressures for functional integration are resulting in large VLSI chips operating at steadily increasing frequencies. The number of long global wires per chip has been continuously increasing with time. These wires carry high-frequency currents and have low resistance. This low resistance is due to the use of thick and wide interconnects at higher metal layers. Additionally, superior conducting materials such as copper have been introduced in order to keep the resistance and the RC delay of global lines small. These factors have led to a continuous increase in the importance of inductance, which has emerged as a standard factor that designers must take into consideration when designing high-performance chips in deep-submicron technologies. In this paper, the authors briefly discuss the importance, physical nature, effects, and extraction issues of on-chip inductance. Understanding the effects of on-chip inductance in high-speed integrated circuits is crucial to high-performance design     

Highly Accurate Quasi-Static Modeling of Coupled Interconnects in CMOS Technology

A new analytic model is presented (the model is based on the induced current density distribution inside silicon substrate) to calculate frequency dependent mutual inductance and resistance per unit length of coupled on-chip interconnects in CMOS technology. The validity of the proposed model has been checked by a comparison with a quasi-TEM spectral domain numerical simulation and equivalent-circuit modeling procedure. It is found that the silicon semiconducting substrate skin effect must be considered for the accurate prediction of the high-frequency characteristics of VLSI interconnects.     

Simulation of high-speed interconnects

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail     

互连线串扰耦合噪声的ABCD矩阵模型

高频互连线间的相互耦合和相互感应是产生串扰的一个重要因素。已有文献利用二端口网络ABCD矩阵从理论上求出了耦合互连线阶跃响应,但该方法对互感描述不准确,导致计算复杂,且对串扰耦合噪声的估计不够准确。该文根据互感的基本定义,修改了原模型中互感的表示方法,提出了一个新的ABCD矩阵级联模型,对LTCC工艺互连线的串扰耦合噪声进行分析,并将得到的ABCD模型分析结果与ADS软件的仿真结果对比,验证了改进的ABCD模型的准确性。     

2001 needs for multi-level interconnect technology

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor)     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

RLC传输线的精确矩模型及其在互连线网时延估计中的应用

快速估计互连线网的信号传输特性是VLSI设计中的重要问题,矩匹配是目前的主要方法.本文给出了获得RLC传输线精确矩模型的一个简单方法,避免了以往方法复杂的推导.文中还提出了互连线时延估计的一个新方法,这一方法不仅可用于目前通常的二阶模型,还可对高阶模型进行估计.