120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.     

Gigabyte/s parallel fiber-optic links based on edge emitting laserdiode arrays

We present a ten-channel parallel fiber optic link consisting of a transmitter based on an edge emitting laser diode array operating nominally at 1 μm wavelength and a complementary receiver based on an InGaAs pin photodetector array. We demonstrate fiber optic link performance up to data rates of 1 Gb/s per channel with low skew at measurement time limited bit error rates lower than 10^-11 over 100 m of multimode fiber ribbon cable. The transmitter is operational, with very clear eye opening, up to baseplate temperatures of 105°C     

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

A 5-6.4 Gb/s transceiver, consisting of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO phase-locked loops (PLLs), and a clock recovery unit, was developed. The Tx has a five-tap pre-emphasis filter, and the Rx has an equalizer with an intersymbol interference (ISI) monitor. Monitoring the ISI enables fine adjustment of loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx compensate for transmission losses of up to 20 dB at 6.4 Gb/s, respectively. Both the Tx and Rx channels, including the PLLs, are 3.92 mm/sup 2/ in area. The transmitter dissipates 150 mW/channel at 6.4 Gb/s when compensating for a loss of 20 dB, and the receiver 90 mW/channel when compensating for the same loss.     

15 Gb/s multichannel optical interconnect laser array transmitteroperating at λ=1.3 μm

We have fabricated and measured detailed bit error rate experiments on a 12 channel optical interconnect transmitter operating at rates up to 1.25 Gb/s per channel, using InGaAsP/InP λ=1.3 μm lasers. The lasers are highly uniform, the channel crosstalk is less than 1 dB, and the mode selective losses are low (<1 dB). This transmitter has been demonstrated in an architecture which would allow the transmission of 120 channels of 100-Mb/s uncompressed video signals     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

Board-level optical-to-electrical signal distribution at 10 gb/s

An opto/electrical prototype for on-board optical-to-electrical signal broadcasting operating at 10 Gb/s per channel over an interconnect distance of 10 cm is demonstrated. An improved 1/spl times/4 multimode interference (MMI) splitter at 1550 nm with linearly tapered output facet is heterogeneously integrated with four p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board with four receiver channels. A novel fabrication/integration approach demonstrates the simultaneous alignment between the four waveguides and the four PDs during the MMI fabrication process. The entire system is fully functional at 10 Gb/s.     

PCB-compatible optical interconnection using 45/spl deg/-ended connection rods and via-holed waveguides

In this paper, a new architecture for a chip-to-chip optical interconnection system is demonstrated that can be applied in a waveguide-embedded optical printed circuit board (PCB). The experiment used 45/spl deg/-ended optical connection rods as a medium to guide light paths perpendicularly between vertical-cavity surface-emitting lasers (VCSELs), or photodiodes (PDs) and a waveguide. A polymer film of multimode waveguides with cores of 100/spl times/65 /spl mu/m was sandwiched between conventional PCBs. Via holes were made with a diameter of about 140 /spl mu/m by CO/sub 2/-laser drilling through the PCB and the waveguide. Optical connection rods were made of a multimode silica fiber ribbon segment with a core diameter of 62.5 and 100 /spl mu/m. One end of the fiber segment was cut 45/spl deg/ and the other end 90/spl deg/ by a mechanical polishing method. These fiber rods were inserted into the via holes formed in the PCB, adjusting the insertion depth to locate the 45/spl deg/ end of rods near the waveguide cores. From this interconnection system, a total coupling efficiency of about -8 dB was achieved between VCSELs and PDs through connection rods and a 2.5 Gb/s /spl times/ 12-ch data link demonstrated through waveguides with a channel pitch of 250 /spl mu/m in the optical PCB.     

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

Development of system specification for laser-optimized 50-/spl mu/m multimode fiber for multigigabit short-wavelength LANs

This paper presents the scientific arguments used in the specification development process by the Telecommunications Industry Association (TIA) Working Group FO-2.2.1 to develop the new multimode fiber and vertical-cavity surface-emitting laser specifications for high-speed application in data communications. Numerous engineering and commercial tradeoffs are described. The specification minimizes the link failure rate and overall link cost through utilization of communication-theory-based modeling and experimental verification. This was balanced against the reality of manufacturing costs attempting to maximize the yield of individual link components. The specific application used as an example has 50-/spl mu/m graded-index multimode fiber operating at 10 Gb/s (e.g., 10 Gb/s Ethernet and fiber channel). The link performance is determined by the interaction of the fiber intermodal dispersion measured by the differential modal delay, and the transceiver launch distribution into the multimode fiber measured by encircled flux. A theoretically based model and the simulation approach that were used to simulate 40 000 links are described. The information from these simulations was used to determine the specification limits. In addition, sensitivity to the specification limits was evaluated. The experimental results of a round robin conducted by the TIA are presented, which confirm that the modeled performance would yield the expected results in actual practice.     

Multimode optical demultiplexer for DWDM with liquid crystal enabled functionalities

We have developed a liquid-crystal-based multimode optical demultiplexer (DEMUX) with additional functionalities such as switching and power equalization. Demultiplexing 16-channel 100-GHz-spaced signals into a 62.5-/spl mu/m multimode-fiber array is demonstrated. The central wavelength of each channel is designed according to the International Telecommunication Union grid. Adjacent channel crosstalk is less than -30 dB. The average 1and 3-dB passbands of the DEMUX are 12.5 and 22.5 GHz, respectively. A maximum extinction ratio of 16.2 dB is achieved. Different channels can be switched with rise and fall times of /spl sim/10 and /spl sim/70 ms, respectively. The outputs of the channels are equalized to -65 dBm. The variation between different channels reduced from /spl sim/10 dB to less than 0.5 dB.     

Advances in multichannel MultiGbytes/s bit-parallel WDM singlefiber link

For ultra-high-speed single media parallel interconnects, an all optical single fiber WDM format of transmitting parallel bits rather than a fiber ribbon format-where parallel bits are sent through corresponding parallel fibers in a ribbon format, can be the media of choice. Here, we discuss the realization of a multi-km×Gb/s bit-parallel WDM (BP-WDM) single fiber link. The distance-speed product of this single fiber link is more than several orders of magnitude higher than that of a fiber ribbon link. The design of a 12 b parallel channels WDM system operating at 1 Gb/s per channel rate through a single fiber is first presented. Experimental results for a two channel system operating at that rate are given. Further improvement of distance-speed product for the BP-WDM link can be obtained with JPL's newly developed 20 Gb/s per channel laser diode array transmitter. Also, new computer simulation results on how a large amplitude co-propagating pulse may induce pulse compression on all the co-propagating data pulses, thereby improving the shaping of these pulses for a WDM system, are presented and discussed. The existence of WDM solitons is also shown     

Efficient CW lasing and high-speed Modulation of 1.3-/spl mu/m AlGaInAs VCSELs with good high temperature lasing performance

The 1.31-/spl mu/m AlGaInAs vertical-cavity surface-emitting lasers achieved efficient single-mode (SM) continuous-wave lasing at temperatures up to 120/spl deg/C, with 2.0-mW output power and 31% slope efficiency, as well as multimode (MM) lasing with up to 9-mW output power and up to 39% slope efficiency. High-speed modulation at data rates up to 10 Gb/s and transmission through different lengths of SM and MM fiber are demonstrated.     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.     

Parallel optical transmitter module using angled fibers and a V-grooved silicon optical bench for VCSEL array

We propose an advanced structure of optical subassembly (OSA) for packaging of the vertical-cavity surface-emitting laser (VCSEL) array, using (111) facet mirror of the V-groove ends formed in a silicon optical bench (SiOB) and angled fiber apertures. The feature of our OSA can provide a low optical crosstalk between neighboring channels, a low feedback reflection, and a large misalignment tolerance along the V-groove. We describe the optimized design of fiber angle, VCSEL position, and fiber position. The fabricated OSA structure consists of 12 channels of angled fiber array, 54.7/spl deg/ V-grooves, Au-coated mirrors on (111) end facet of the V-grooves, and flip-chip-bonded VCSEL array on a SiOB. In this structure, the beam emitted from the VCSEL is deflected at the 54.7/spl deg/ mirror of (111) end facet and propagated into the angled fiber. The angled fiber array was polished by 57/spl deg/. Fabricated OSAs showed a coupling efficiency of 30%-50% that is 25 times larger than that obtained from an OSA with a vertically flat fiber array. Our OSA showed large misalignment tolerance of about 90 /spl mu/m along the longitudinal direction in the V-groove. We fabricated a parallel optical transmitter module using the OSA and demonstrated 12 channels /spl times/2.5 Gb/s data transmission with a clear eye diagram.     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter

A 4:1 SERDES IC suitable for SONET OC-192 and 10-Gb/s Ethernet is presented. The receiver, which consists of a limiting amplifier, a clock and data recovery unit, and a demultiplexer, locks automatically to all data rates in the range 9.95-10.7 Gb/s. At a bit error rate of less than 10/sup -12/, it has a sensitivity of 20 mV. The transmitter comprises a clock multiplying unit and a multiplexer. The jitter of the transmitted data signal is 0.2 ps RMS. This is facilitated by a novel notched inductor layout and a special power supply concept, which reduces cross-coupling between the transmitter and receiver. Integrated in a 0.13-/spl mu/m CMOS technology, the total power consumption from both 1.2- and 2.5-V supplies is less than 1 W.     

Parallel optical interconnection for uncoded data transmission with1 Gb/s-per-channel capacity, high dynamic range, and low powerconsumption

The design, realization, and characterization of a multichannel dc-coupled ECL-voltage compatible parallel optical interconnection with a bit rate of up to 1 Gb/s-per-channel is reported. The transmitter module consists of an array of laser diodes with low threshold currents and the 50 Ω matching network, the receiver module of a photo diode array and an amplifier array. All the opto-electronic and electronic components are fabricated as arrays with a pitch of 250 μm. The total power consumption is 110 mW per channel, For a BER <10¹⁴ the dynamic range is 15 dB for a bit rate per channel of 200 Mb/s, 13 dB for 630 Mb/s, and 8 dB for 1 Gb/s. The channel crosstalk is below -48 dB (electrical). The size of the opto-electronic parts (12 channels, without electrical connectors) is only 10 mm (length)×5 mm (width)×4 mm (height)     

High-gain SiGe transimpedance amplifier array for a 12/spl times/10 Gb/s parallel optical-fiber link

A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 /spl mu/A/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12/spl times/10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools.