可编程逻辑阵列（PLA）自动版图生成器

可编程逻辑阵列ＰＬＡ自动版图生成器可以使设计者快速地得到宏单元，从电路盒物理版图的细节中解放出来，因ＰＬＡ较低的设计费用和可编程的特点，生成器对于实现电路中的控制部分十分有效，ＰＬＡ自动版图生成器在国内首次实现了ＰＬＡ由逻辑输入到版图生成的自动设计。     

一个电路版图自动设计系统

本文描述一个电路版图的自动设计系统。它将具有高级设计描述的模块分解成规模较小、易处理的单元，通过对单元进行平面规划、合理安置和多次转换后，自动地产生这些单元版图的ＣＩＦ文件。这是一个完全自动地将高级设计描述的电路转换成电路几何描述的过程．     

SG765A型车速报警电路的设计与应用

介绍了ＳＧ７６５Ａ的版图设计以及该电路的主要特点和性能，并给出了其典型应用。重点介绍了ＳＧ７６５Ａ汽车速度报警的原理。     

9×64位译码器专用集成电路的芯片设计

介绍了一专用集成电路ＣＳＣ７１０７０译码器电路的芯片设计。这套电路分为两个芯片。采用３μｍ硅栅ＣＭＯＳ标准单元设计系统进行设计。利用ＷＯＲＫＶＩＥＷ软件在微机上进行逻辑输入，转换成网表文件在ＰＲＩＭＥ上设计版图。版图设计采取全人工布局，自动通道布线方式。该电路采用逻辑模拟和设计验证两种方式检验设计的正确性。     

EPLD可编程逻辑器件及应用

美国ＡＴＭＥＬ公司生产ＥＰＬＤ可编程器件有多年的历史，器件型号多样，且已经应用到各行业的电子电路系统中。文章就使用ＡＴＶ２５００器件实现一个分频移相电路的实际例子，说明ＥＰＬＤ的设计过程。     

可编程逻辑器件在测控电路中的应用与设计

本文论述了在测控电路中使用可编程逻辑器件（ＰＬＤ）的意义与优越性；利用逻辑设计软件ＡＢＥＬ进行了大型变压器油温控制器通用阵列逻辑（ＧＡＬ）的设计与开发。     

具有边界约束的LSI模块版图自动生成系统

本文介绍了一个具有边界约束的大规模集成电路模块版图自动生成系统（ＡＭＧＣ）。ＡＭＧＣ的输入为模块的电路网表，输出为模块的ＣＭＯＳ版图数据。由ＡＭＧＣ自动生成的版图既符合用户的设计规则，也符合模块输入输出端口位置及长宽比等用户给出的约束条件。     

人机结合改善标准单元芯片设计

介绍了一种专用译码电路的芯片设计。该电路采用正向设计方法，共设计主要表现为两个方面；逻辑电路设计和版图设计。简单介绍了电路的逻辑设计；详细描述了采用人机结合的方式，在自动布局布线系统设计的基础上进行人工干预的版图设计方法。     

一种基于厚膜工艺的电路版图设计

在电子线路版图设计中,通常采用印刷线路板技术。如果结合厚膜工艺技术,可以实现元器件数目繁多,电路连接复杂,且安装空间狭小的电路版图设计。通过对3种不同电路版图设计方案的理论分析,确定了惟一能满足要求的设计方案。基于外形尺寸的要求,综合考虑电路的性能和元件的封装形式,通过合理的电路分割和布局设计,验证了设计方案的合理性和可实现性。体现了厚膜工艺技术在电路版图设计中强大的优越性,使一个按常规的方法无法实现的电路版图设计问题迎刃而解。     

中频接收电路的版图设计

中频接收电路的版图设计一般会采用Cadence版图设计工具。版图的设计包括单元库建立、平面布置和布局、细节布线和全局布线以及DRC和LVS规则检查。文章将主要从这四个方面阐述中频接收电路的版图设计。     

DoDAF体系结构框架研究

体系结构设计是一种重要的系统顶层设计方法,是保证系统之间可集成可互操作的关健。美军在已有体系结构框架及支撑技术的研究基础上,制定了全面的体系结构框架及相关领域的发展规划,大力推进体系结构的开发与应用。分析美国国防部体系结构框架DoDAF及其最新2.0版,对于我军信息系统的建设非常有意义。     

1 µm MOSFET VLSI technology: Part III—Logic circuit design methodology and applications

Logic circuits were designed and fabricated in a 1 µm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional "Weinberger" layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21- ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.     

A programmable CORDIC chip for digital signal processingapplications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences     

机载任务电子系统总体布局优化设计

在机载任务电子系统结构总体设计中应用系统布局优化设计方法,主要包括舱外天线布局优化和舱室系统布局优化两方面内容,优化方法涉及到多学科优化算法、改进的遗传算法等。该方法对于任务电子系统结构总体设计能够起到系统理论指导作用,通过该方法能够有效提升任务电子系统综合性能。     

1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.     

Integrated facility layout and material handling system design insemiconductor fabrication facilities

Semiconductor manufacturing is an important component of the U.S. manufacturing industry. Most of today's fabrication facilities and those being designed for the near future use a bay layout configuration and an overhead monorail system for moving material between bays. These material handling systems are usually designed with a spine or perimeter type of configuration. This paper investigates the layout and material handling system design integration problem in semiconductor fabrication facilities and proposes a methodology for solving this integrated design problem. A spacefilling curve approach is used to address the facility layout, while the structure of the spine and perimeter configurations are exploited to create a network flow problem to determine the material handling system design. Computational results are presented and show exceptional promise for this procedure in solving the integrated design problem in a semiconductor manufacturing environment     

Computer-aided design for integrated circuits: trying to bridge the gap

CAD performance in the field of simulation, testing, and layout is compared to the increase of digital integrated systems complexity. This complexity already exceeds the fundamental limits of existing software, especially in the testing area. On the other hand, fully manual layout of VLSI leads to unreasonably long design times and extremely high risks. This will favor design automation methods in layout. Testability and layout will most likely impose some sacrifice of VLSI overcapacity to a more structured system architecture. This architecture will lead to testable dedicated VLSI system design through the use of automated design software to keep development costs low.     

航天测量船测控系统结构总体设计

讨论了航天测量船测控系统结构总体设计,包括天线布局、机房布局、供电、照明、接地、电缆的分类及布局、关键结构问题等方面,并给出了解决方案。