A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Simulation of Active-Matrix Electrophoretic Display Response Time Optimization by Dual-Gate a-Si:H TFT With a Common Gate Structure

Large off-state drain-source current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) pixel leads to dramatic data voltage degradation, which causes severe crosstalk and undesired large response time. In this paper, the leakage current influence on response time is investigated and simulated. A compact model of response time t versus off-state drain-source current I _off is established. The simulation result induces that by reducing I _off the response time can be efficiently shorted. In order to reduce the off-state current, dual-gate amorphous silicon (a-Si:H) TFT with a common gate structure is discussed. Its current regulation mechanism is illustrated, and its fitness for driving the AMEPD pixel is explained. The SPICE simulation results prove that except reducing the crosstalk, dual-gate a-Si TFT can also significantly short the response time by cutting down the off-state current under the operation conditions of AMEPD application, while insignificantly reduces the on-state current.     

Predicting Method of Leakage Current in Multiple-Gate Amorphous Silicon TFTs for Active-Matrix Electrophoretic Displays

The large off-state drain–source leakage current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) may cause severe crosstalk and long pixel refresh time. Multiple-gate amorphous silicon TFT (a-Si TFT) is a common use to overcome this issue. In this paper, we show that the leakage current of multiple-gate a-Si TFT can be computed from the $I$–$V$ characteristics of a single TFT by an analytical current model. The predicted leakage currents show good agreement with the expected values in SPICE simulation. This model is also applicable for the multiple-gate a-Si TFTs used in other high voltage driven devices.      

Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs

This letter presents a novel pixel circuit for hydrogenated amorphous silicon (a-Si:H) active matrix organic light-emitting diode displays employing the short-term stress stability characteristics of a-Si:H thin film transistors (TFTs). The pixel circuit uses a programming TFT that is under stress during the programming cycle and unstressed during the drive cycle. The threshold voltage shift (V/sub T/-shift) of the TFT under these conditions is negligible. The programming TFT in turn regulates the current of the drive TFT, and the pixel current therefore becomes independent of the threshold voltage of the drive TFT.     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

A high performance thin-film transistor using a low temperaturepoly-Si by silicide mediated crystallization

Electric field enhanced silicide mediated crystallization (SMC) was introduced for low-temperature polycrystalline silicon thin-film transistors (TFTs) on glass substrates. The amorphous silicon (a-Si) film having an average Ni thickness of 0.15 Å, was completely crystallized at a temperature of 480°C within 30 min in the presence of an electric field of 40 V/cm. The poly-Si is composed of needlelike crystallites with a few μm length and about 50 nm width. The poly-Si TFT using the SMC exhibited a field effect mobility of 86 cm²/Vs, a threshold voltage of -0.6 V, and a subthreshold slope of 0.6 V/dec     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

A new a-Si:H TFT pixel circuit compensating the threshold voltage shift of a-Si:H TFT and OLED for active matrix OLED

We propose a new hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel circuit for an active matrix organic light-emitting diode (AMOLED) employing a voltage programming. The proposed a-Si:H TFT pixel circuit, which consists of five switching TFTs, one driving TFT, and one capacitor, successfully minimizes a decrease of OLED current caused by threshold voltage degradation of a-Si:H TFT and OLED. Our experimental results, based on the bias-temperature stress, exhibit that the output current for OLED is decreased by 7% in the proposed pixel, while it is decreased by 28% in the conventional 2-TFT pixel.     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator