Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V     

A switched-current, switched-capacitor temperature sensor in0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT δV_BE signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25° from -55°C to 125°C with an error of less than 1°. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 μA. The supply voltage is 2.7-5.5 V     

Linearity performance comparison of cascode current source and single-device current source IDPs; analyses,simulations and measurements

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input.     

A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.     

Extension of the common-mode range of bipolar input stages beyondthe supply rails of operational amplifiers and comparators

When the input voltage of an operational amplifier or comparator with a bipolar input stage exceeds the range of normal operation, the polarity of the output signal reverses and the input bias current increases to excessively large values. Saturation of the input transistors restricts the sensing of differential voltages to a common-mode (CM) range roughly between the positive and the negative supply rails. Input stage configurations that not only provide solutions to prevent the signal reversal and the excessive increase of input bias current, but also provide an extension of the CM range far beyond the supply rails, while the transconductance for differential input voltages remains constant, are described. Integrated implementations of the input stages realized a CM range reaching +15 V at a single supply voltage as low as 1 V, while the input bias current was limited to 6 μA     

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-V_t MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 μm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8 and −0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.     

一种电容阵列结构的10位8通道1MS/s逐次逼近AD转换器

设计了一种用于多电源SoC的10位8通道1MS/s逐次逼近结构AD转换器。为提高ADC精度,DAC采用改进的分段电容阵列结构。为降低功耗,比较器使用了反相器阈值电压量化器,在模拟输入信号的量化过程中减少静态功耗产生。电平转换器将低电压数字逻辑信号提升为高电平模拟信号。采用UMC 55nm 1P6M数字CMOS工艺上流片验证设计。测试结果表明,当采样频率为1 MS/s、输入信号频率为10 kHz正弦信号情况下,该ADC模块在3.3 V模拟电源电压和1.0 V数字电源电压下,具有最大微分非线性为0.5LSB,最大积分非线性为1LSB。测得的SFDR为75 dB,有效分辨率ENOB为9.27位。     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-icm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages.The ADC is realized in the 0.13-tt,m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage.Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage,such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm2.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter(ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic device...     

一种具有失配校准技术的轨到轨输入逐次逼近型模数转换器设计

传统的逐次逼近型模数转换器很难对输入等于电源电压的模拟信号进行正确的模数转换,本文提出了一种新型的逐次逼近型模数转换器,能够对输入幅度等于电源电压的输入信号进行正确的转换,并且具有用于缩短采样时间的采样保持放大器电路,同时针对比较器失调和电容阵列失配提出了校准技术,进一步提高了转换精度。测量结果显示该模数转换器的最大信噪谐波失真比可以达到72dB,有效输入信号带宽为1.25MHz,消耗功耗为1mW,相应的FOM指数为123fJ。     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

流水线模数转换器研究现状

基于运算放大器(OTA)的开关电容技术是目前流水线模数转换器(ADC)的主要实现方式.由于该技术需要使用高增益宽带宽OTA来保证电路的速度和精度,基于该技术的流水线ADC难以在纳米级CMOS工艺条件下实现并且功耗限制日益突出.文章首先介绍了流水线ADC的基本原理,其次介绍了基于OTA的开关电容实现技术及其在纳米级CMO...     

一种ADC电源方案设计与电源完整性分析

为合理利用机箱空间、减少电源芯片使用数量,提出了一种20片模数转换器(Analog-to-Digital Converter,ADC)芯片供电方案,既可减小不同频段ADC芯片因输入相同电源造成信号干扰的可能,也可减少低压差线性稳压器(Low Dropout Linear Regulator,LDO)的使用数量,充分利用电源芯片的供电能力,大大降低了模块开发成本。与传统电源方案相比,该方案中电源芯片使用数量减少一半,电源布局面积缩小60%。同时通过仿真可提前识别出其中一路LDO芯片输出的2.5 V电压在到达ADC芯片时未能达到ADC芯片输入的最小电压要求。结合静态压降公式提出3种优化方法,均可达到ADC芯片输入的最小电压要求。采用第2种优化方法,回板实测结果显示3个芯片接收到的电源电压差值为0.3 V,与仿真结果一致。     

A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC.     

一款结合数字校正技术的流水线ADC设计

基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。     

A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology

A novel low-voltage rail-to-rail parallel time-based analog-to-digital converter (ADC) is proposed. The proposed ADC works like a conventional flash ADC except that the process is performed in the time-domain. Since the operation of analog integrated circuits at low supply voltages is limited, converting the voltage signals to the time domain improves the efficiency of the circuit. In this paper, a constant-delay ladder is utilized to make the reference delay-times to compare with the input signal. A 1-V 5-bit 500 MS/s ADC has been designed and simulated in 0.18 µm CMOS technology consumed 3.66 mW. The simulation results show 0.3lsb and 0.2lsb for INL and DNL respectively. Signal-to-noise and distortion ratio (SNDR) of the proposed ADC is 26.7 dB at Nyquist frequency. The rail-to-rail operation and linearity of the voltage-to-time converter (VTC) improved the efficiency of the ADC comparing to the similar time-based ADCs. The figure-of-merit (FoM) of the ADC is about 0.31 (pJ/conv.step).

     

Technique for offset voltage cancellation in MOS operational amplifiers

A novel technique for the continuous-time removal of the input offset voltage in operational amplifiers is presented. This scheme converts a conventional op-amp into a similar differential-in/differential-out op-amp with zero differential input offset voltage. The nonzero common-mode input offset voltage can be isolated using a sampled-data time-averaging technique and minimised by negative feedback.     

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs

This paper presents a design-for-diagnosis method to identify error sources in pipelined analog-to-digital converters (ADCs). In the proposed method, the stage under test (SUT) is configured to separate each error effect contained in its output residual signal. Two stages after the SUT are configured as a cyclic ADC to digitize the residual output voltage of the SUT. Critical circuit parameters, namely, op-amp gain, capacitor mismatch, op-amp offset, and comparator offset, are identified in the digital domain. Accurate analog test input signals are not necessary for the proposed design-for-diagnosis scheme. A simple digital decoder is employed to generate test control signals. Several additional switches are used to perform SUT re-configuration, which induce minor area overhead. Behavioral and circuit simulations are performed to show the effectiveness of the proposed method.     

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail- to-rail input and output swing. The current headroom is 3???A and the supply voltage is 300?mV. For supply voltages down to 300?mV simulated data shows that the maximum clock frequency is approximately 600?MHz.