A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines     

An acoustic charge transport digitally programmable transversalfilter

A monolithic 64-tap digitally programmable analog transversal filter is described that uses an acoustic charge transport (ACT) tapped delay line and integrated GaAs MESFET circuits for coefficient storage and tap weight circuitry. The device has 6-b tap weights, an input sampling rate of 360 MHz, and an output tap spacing corresponding to an output sampling rate of 130 MHz. This results in the effective execution of 8×10⁹ multiply and sum operations per second in a 38-mm² chip that dissipates less than 2 W. This effective computational rate is limited in the present design by the spacing of the ACT delay line taps, which is dictated by the geometry of the tap weight circuits. The chip uses fully random-access tap weight memory, which is easier to interface to typical digital controllers than the usual shift-register storage approach. Tap address and tap weight data are applied as parallel 6-b words, and the data work is clocked into the address location by the application of an enable pulse. The tap weight circuits use monolithic capacitors and GaAs MESFET analog switches to realize a multiplying converter based on a C/2C ladder configuration with a sign-and-magnitude tap weight word format. A ladder accuracy of 7 b is achieved by compensating the ladder component values for parasitics     

A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path

A micropower chopper stabilized opamp is presented. The new topology incorporates a switched capacitor filter with synchronous integration inside the continuous time signal path virtually eliminating chopping noise. A three-stage amplifier with multipath nested Miller compensation is modified to incorporate chopping of the input stage, sinc filtering to notch any chopping ripple, and a compensation scheme to maintain an undistorted high-speed signal path. Characteristics of the amplifier presented include rail to rail input and output operating on supplies of 1.8 to 5.5 V over -40degC to 125degC. Quiescent supply current is 17 muA, input offset is 3 muV, input offset drift is 0.02 muV/degC, GBW is 350 kHz, and the chopping frequency is 125 kHz. Die area is 0.7 mm² using a precision analog mixed-signal CMOS process combining low-noise 0.6-mum analog transistors with 0.3-mum digital CMOS capability     

Mixed-signal quadrature demodulator with a multicarrierregeneration system

This paper presents a combined analog/digital demodulation system built around a (PLL) with digital carrier regeneration. The input signal itself is not digitized, but the PLL is digital wherever it is possible. The link between the analog and the digital domain is a 1-bit sigma-delta converter that converts the (quasi-dc) output signal of the PLL's phase detector into a bitstream. The PLL's loop filter doubles as a decimation filter for the bitstream. The analog I and Q output signals are obtained by multiplying the analog input signal with the digital output signal of the PLL in two four-quadrant multiplying digital-to-analog converters     

The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided.     

Design and characterization of a real-time correlator

The design and characterization of a real-time correlator/electrically programmable transversal filter is presented, based on a novel functional multiplying structure in a standard single-level MOS LSI process. The analog information is sampled and held at fixed sites on the chip and the tap weights slide past them; the taps are digitized into 7 bits which control the selection of seven binary area-ratioed MOS capacitors per tap position. The rotation of the tap weights can reduce the effect of tap-weight errors but contributes to fixed pattern noise. Experiments using cascaded chips to build longer filters show excellent transfer-function agreement with theory. Dynamic range of the device is limited primarily by fixed pattern noise. This problem has been modeled and at present about a 45-dB dynamic range has been obtained for the heaviest doped chips when driven by input-signal amplitudes which allow better than 1-percent harmonic distortion. With improvements suggested, significant increases are expected in the dynamic range of the device.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

A 4 Gsample/s 2 bits flash ADC with 2–4 GHz input bandwidth for radio astronomy applications

This paper presents the design and the measurement results of a high speed A/D converter (ADC or digitizer) developed for radio-astronomy applications and especially for the ALMA (Atacama Large Millimeter Array) project. This monolithic digitizer is implemented in a BiCMOS 0.35 μm SiGe process for high frequency mixed-signal applications. The main characteristics of this circuit are a 2 bits resolution with 3 quantization levels (equivalent to 1.5 bits) with 4 Gsample/s rate, a wide input bandwidth from 2 GHz up to 4 GHz under full Nyquist condition. The adopted digitizer architecture is that of a conventional flash analog to digital converter structure. The overall chip dissipates 652 mW under ± 1.25 V supply and the die area is 5.4 mm².     

A programmable transversal filter for voice-frequency applications

A fully integrated, programmable transversal filter optimized for low-noise, low-power, voice-frequency applications is described. The filter, fabricated with a standard double-poly NMOS process, achieves convolution of an analog input signal with digital tap weightings using a structure with sample-and-hold gates for analog storage and a multiplexed MDAC for multiplication. The design of the filter eliminates fixed pattern noise usually associated with such structures and enables a dynamic range in excess of 70 dB (LPF, f/SUB o//f/SUB s/=0.08) to be achieved at an 8 kHz sampling rate with a power dissipation of less than 80 mW. This area efficient device forms the basis for a range of possible voice-band signal processing functions.     

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drivesin 2-μm CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-μm CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm² and dissipates 165 mW     

A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation

A continuous-time system that converts its analog input to a continuous-time digital representation without sampling, then processes the information digitally without the aid of a clock, is presented. Without sampling there is no aliasing, which reduces the in-band distortion power by not aliasing into band out-of-band distortion components. The 8-bit system, fabricated in a 90 nm CMOS process, utilizes continuous delay elements as part of a programmable transversal FIR filter. The input is encoded by a delta modulator without a clock into a series of non-uniformly spaced tokens, which are processed by the digital continuous-time filter and converted to an analog output using a custom DAC that guarantees there are no glitches in the output waveform. All activity is signal driven, automatically affording dynamic power scaling that tracks input activity.      

Multirate analog-digital systems for signal processing andconversion

Systems containing both analog and digital functions have been investigated with the purpose of realizing mixed-signal integrated circuits with higher levels of functionality and integration. In most cases, such mixed-signal systems are inherently multirate because of the different sampling rates employed at various stages of the system. The multirate concepts have been used for traditional applications, such as subband coding and narrowband filter design. Some unconventional applications of multirate signal processing are also emerging, both for converting between analog samples and digital words, and for realizing processing functions in an easier and more economical way than would be possible using purely digital or analog techniques. This paper reviews fundamental multirate concepts, discusses some developments in this area of integrated multirate analog-digital systems, and outlines some possible future directions for research and application     

A Rank Encoder: Adaptive Analog to Digital Conversion Exploiting Time Domain Spike Signal Processing

An electronic circuit is presented that encodes an array of analog input signals into a digital number. The digital output is a rank order code that reflects the relative strength of the inputs, but is independent of the absolute input intensities. In that sense, the circuit performs an adaptive analog to digital conversion, adapting to the average intensity of the inputs (i.e. effectively normalizing) and adapting the quantization levels to the spread of the inputs. Thus, it can convey essential information with a minimal amount of output bits over a huge range of input signals.As a first processing step the analog inputs are projected into the time domain, i.e. into voltage spikes. The latency of those spikes encodes the strength of the input. This conversion enables the circuit to conduct further analog processing steps by asynchronous logic.     

新型电容式MEMS加速度计数字接口电路设计

MEMS加速度计接口电路主要采用传统sigma-delta架构实现,但这种方式中的电路失调电压很容易产生积分饱和现象．为解决这个问题,本文设计了一种可以用于钻井、石油勘探等微弱信号检测的新型数字电容接口电路．该设计在电容式MEMS加速度传感器基础上,采用FPGA实现数字三阶环路滤波器,构成5阶sigma-delta系统．采用数字环路滤波器降低了ASIC模拟电路版图设计与芯片测试难度,利于快速优化环路滤波器设计参数,改善系统稳定性和优化系统噪声性能．前置放大器采用一种相对简单的相关双采样技术,能够有效减小前置放大器的失调电压．根据MEMS加速度计前置放大器输出信号符合正态分布的特点,设计了带有一定预测功能的8-bit瞬时浮点ADC,实现模拟与数字环路滤波器互联．在200Hz带宽内,该接口电路系统噪声基底达到53．09ng／rt（Hz）,满足系统噪声设计要求．前置放大器与ADC采用XFAB XH018混合信号CMOS工艺流片,开环测试表明,前置放大器的灵敏度和噪声分别为0．69V／pF和3．20μV／rt（Hz）．     

FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems

A field-programmable-gate-array (FPGA)-based built-in self-test (BIST) approach that is used for adaptive control in mixed-signal systems is presented. It provides the capability to perform accurate analog functional measurements of critical parameters such as the third-order intercept point, frequency amplitude and phase responses, and noise figure. The results of these measurements can then be used to adaptively control the analog circuitry for calibration and compensation. The BIST circuitry consists of a direct digital synthesizer-based test pattern generator and a multiplier/accumulator-based output response analyzer. The BIST approach has been implemented in an FPGA-based mixed-signal system and used for actual analog functional measurements. The BIST measurements agree quite well with the results obtained with the traditional analog test equipment. The proposed BIST circuitry provides a unique means for high-performance adaptive control in mixed-signal systems.     

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma–delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-${rm mu}{hbox{m}}$ CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.      

Toward Wide-Band High-Resolution Analog-to-Digital Converters Using Hybrid Filter Bank Architecture

The paper presents the problem of design and simulation of a high-speed wide-band high-resolution analog-to-digital (ADC) converter working in a bandpass scenario. Such converters play a crucial role in software-defined radio and in cognitive radio technology. One way to circumvent the limits of today’s ADC technologies is to split the analog input signal into multiple components and then sample them with ADCs in parallel. The two main split approaches, time interleaved and frequency splitting, can be modeled using a filter bank paradigm, where each of these two architectures requires a specific analysis for its design. In this research, the frequency splitting approach was implemented with the use of a hybrid filter bank ADC, which requires an output digital filter bank perfectly matched to the input analog filter bank. To achieve this end, an analog transfer function, together with an assumption of strictly band-limited input signal, has been used to design the digital filter bank so far. In contrast, the author proposes dropping the band-limit assumption and shows that the out-of-band input signal has to be taken into account when designing a hybrid filter bank.     

Comparative logic figure of merit of current high-speed transistors

A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated.     

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW