An FPGA implementation for neural networks with the FDFM processor core approach

This paper presents a field programmable gate array (FPGA) implementation of a three-layer perceptron using the few DSP blocks and few block RAMs (FDFM) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input–hidden–output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs and 9676 slices. It runs in 242.89 MHz clock frequency, and a single evaluation of 150 nodes perceptron can be performed 1.65 × 10⁷ times per second.     

Testing interconnections to static RAMs

A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that strictly conforms to IEEE 1149.1. Test operation is more efficient, requiring a third of the number of scan operations. A test-pattern set and a method for detecting and diagnosing the interconnection faults on RAMs are also described. The test-pattern set can be enhanced as necessary to increase coverage and diagnosing ability and to handle any RAM configuration. The implementation of the proposed boundary-scan register is independent of the test algorithm used. It is believed that the methodology is extendable to RAMs that use an access protocol different from the one described, for example dynamic RAMs and synchronous RAMs     

Using the page mode of dynamic RAMs to obtain a pseudo cache

A method of using dynamic RAM chips is described that may result in a significant reduction in their access and cycle time, at the expense of some extra control logic. This reduction is achieved by not having to perform a row access. This paper deals first with the properties of dynamic RAMs and the relevant terminology. The basics of caches are introduced and applied to dynamic RAMs. An implementation example is given and the improvement in access and cycle time is analysed.     

用高速DSP构成图像识别专用系统的研究与设计

本文介绍用高速DSP芯片TMS32010、单片机8031、便携式扫描器HS-3000构成的一种脱机图像识别专用系统。系统为主从式,并行处理。应用于印鉴、商标的真伪识别,及指纹、手写体汉字的识别。速度高;处理能力强;性能价格比高。64KB外部RAMs的扩充,像素存放RAMs的切换,“0”号单元的程序转储,基本库区、主从系统的通讯接口等电路的设计,优化了系统整体结构。     

New Products

Teradyne's J387A for testing dynamic and static RAMs, ROMs, and PROMs features half-nsec accuracy at the pins of the memory under test, a pattern generator testing dynamic RAMs at an unrestricted 20 MHz, and 16 independent timing sets for testing five-volt, address-multiplexed, page-mode memories.     

When Can Limited Randomness Be Used in Repeated Games?

The central result of classical game theory states that every finite normal form game has a Nash equilibrium, provided that players are allowed to use randomized (mixed) strategies. However, in practice, humans are known to be bad at generating random-like sequences, and true random bits may be unavailable. Even if the players have access to enough random bits for a single instance of the game their randomness might be insufficient if the game is played many times. In this work, we ask whether randomness is necessary for equilibria to exist in finitely repeated games. We show that for a large class of games containing arbitrary two-player zero-sum games, approximate Nash equilibria of the n-stage repeated version of the game exist if and only if both players have Ω(n) random bits. In contrast, we show that there exists a class of games for which no equilibrium exists in pure strategies, yet the n-stage repeated version of the game has an exact Nash equilibrium in which each player uses only a constant number of random bits. When the players are assumed to be computationally bounded, if cryptographic pseudorandom generators (or, equivalently, one-way functions) exist, then the players can base their strategies on “random-like” sequences derived from only a small number of truly random bits. We show that, in contrast, in repeated two-player zero-sum games, if pseudorandom generators do not exist, then Ω(n) random bits remain necessary for equilibria to exist.     

A hardware digital fuzzy inference engine using standard integrated circuits

The paper describes a general-purpose board-level fuzzy inference engine intended primarily for experimental and educational applications. The components are all standard TTL integrated circuits (7400 series) and CMOS RAMs (CY7C series). The engine processes 16 rules in parallel with two antecedents and one consequent per rule. The design may easily be scaled to accommodate more or fewer rules. Static RAMs are used to store membership functions of both antecedent and consequent variables. “Min-max” composition is used for inferencing, and for defuzzification, the mean of maxima strategy is used. Simulation on VALID CAE software predicts that the engine is capable of performing up to 1.56 million fuzzy logic inferences per second.     

Does indirect addressing matter?

In the study of random access machines (RAMs) and the complexities associated with their algorithms, the availability of indirect addressing often creates an analysis obstacle. We show that for RAMs equipped with a sufficiently rich set of basic operations, indirect addressing does not increase computational power, and can be simulated either in linear time or on-line in real time. These results pertain to the uniform cost model and, particularly, assume a unit cost variable shift.     

机载计算机RAM故障诊断技术

针对RAM的典型故障模式,以及机载计算机RAM按字寻址的特点,通过对基于字的March C-算法的优化并结合所提出的隔行隔单元跳变的RAM的故障诊断算法,实现了RAM典型故障的全面检测。并以A340飞机主飞行控制计算机为例,对所提出的算法的执行效率进行了分析。结果表明,所提出的存储器故障诊断算法执行效率高,能够完全满足机载计算机地面上电启动时对存储器故障诊断快速而高效的要求。     

Self-embedding watermark with flexible restoration quality

A novel self-embedding watermarking scheme is proposed, in which the reference data derived from the most significant bits (MSB) of host image and the localization data derived from MSB and reference data are embedded into the least significant bits (LSB) of the cover. At authentication side, while the localization data are used to detect the blocks containing substitute information, the reference data extracted from other regions and the spatial correlation are exploited to recover the principal content in tampered area by a pixel-by-pixel manner. In this scheme, the narrower the tampered area is, the higher quality of recovered content can be obtained.     

CCD Charge-Coupled Device Memories: A Perspective

CCD memories can fill the gap between RAMs and disks. If cost-effective, they will tend to be used in high-end, high-performance computers.     

Hierarchical recovery for tampered images based on watermark self-embedding

In this paper, we propose a new self-embedding watermarking scheme with hierarchical recovery capability. The binary bits in the adopted MSB layers are scrambled and individually interleaved with different extension ratios according to their importance to image visual quality. The interleaved data, which are regarded as reference bits for tampering recovery, are segmented into a series of groups corresponding to the divided non-overlapping blocks, and then embedded into the LSB layers of blocks together with authentication bits of tampering detection. Because the extension ratios of MSB-layer bits are based on the hierarchical mechanism, the efficiency of reference bits is increased, and higher MSB layers of tampered regions have greater probabilities to be recovered than lower MSB layers, which can improve the visual quality recovered results, especially for larger tampering rates. Experimental results demonstrate the effectiveness and superiority of the proposed scheme compared with some of state-of-the-art schemes.     

DCT域半易损水印技术

该文提出了一种DCT域半易损水印技术用于图像内容认证．水印嵌入算法基于DCT域的JPEG压缩不变特性,对一定质量的JPEG压缩是稳健的．水印比特包括认证比特和恢复比特．认证比特是块自嵌入的。可以对不可接受的图像篡改进行准确的检测和定位,而恢复比特则可以对篡改的图像进行一定程度的恢复．该文还分析了DCT变换过程中取整误差的影响,从理论上证明了水印嵌入算法中迭代过程的收敛性．实验结果证明了该半易损水印可以容许一定程度的JPEG压缩和AWGN噪声,对局部发生的篡改可以有效地检测、精确定位并进行内容恢复．     

Electrical characterization of megabit DRAMs. 11. Internal testing

For pt.I. see ibid., vol.8, no.3, p.36-43 (1991). Contactless tools for testing inside dynamic RAMs, including hot-spot detection, emission microscopy, scanning laser microscopy, and submicron electron beam testing, are described. Basic principles and experimental setups are described. The utility of the techniques is assessed     

Constructing a reliable test&set bit

The problem of computing with faulty shared bits is addressed. The focus is on constructing a reliable test&set bit from a collection of test&set bits of which some may be faulty. Faults are modeled by allowing operations on the faulty bits to return a special distinguished value, signaling that the operation may not have taken place. Such faults are called omission faults. Some of the constructions are required to be gracefully degrading for omission. That is, if the bound on the number of component bits which fail is exceeded, the constructed bit may suffer faults, but only faults which are no more severe than those of the components; and the constructed bit behaves as intended if the number of component bits which fail does not exceed that bound. Several efficient constructions are presented, and bounds on the space required are given. Our constructions for omission faults also apply to other fault models     

浅析Cookies认证机制及其安全性

Web服务器生成Cookies并作为文本存贮于用户计算机硬盘或内存中,是实现Web应用认证的主要手段。本文分析了Cookie认证机制的实现过程与特点,并且论述了该认证机制易遭受的安全威胁以及安全需求,并给出实现安全Cookie认证的方法与措施。     

Test algorithms for double-buffered random access andpointer-addressed memories

Test algorithms for static double-buffered RAMs and pointer-addressed memories (PAMs) are presented. The reasons why test algorithms for single-buffered memories are inadequate to test double-buffered memories (DBMs) are discussed. To obtain a realistic fault model, the authors perform an inductive fault analysis on the DBM cells. They also show that the address generation method imposes different requirements on the test algorithms     

Watermarking of digital images in frequency domain

Invisible watermarking methods have been applied in frequency domains, trying to embed a small image inside a large original image. The original bitmap image will be converted into frequency domain to obtain the discrete cosine transform (DCT) matrices from its blocks. The bits of the logo image are embedded in random color components of the original image, as well as in random positions in each selected block. These positions are alternating current (AC) coefficients of the DCT matrix. The randomness is obtained from RC4 pseudorandom bit generator that determines in which color component this logo image bits will be embedded. The embedded bits have been hidden in random blocks in the image, which are chosen according to a (semi-random) function proposed in this work.     

基于Niederreiter编码的混合加密方案的改进

基于编码的密码方案具有抗量子的特性和较快的加解密速度,是当今抗量子密码方案的备用方案之一。现有基于编码的混合加密方案已经达到选择密文攻击不可区分（IND-CCA）安全,其缺点是加密收发双方共享秘密密钥的公钥尺寸较大。针对基于Niederreiter编码的混合加密方案公钥尺寸大的的问题,首先对Niederreiter编码方案的私钥进行随机拆分,然后对Niederreiter编码方案的明文进行随机拆分,最后对Niederreiter编码方案的加解密过程进行了改进。经过分析得出,改进方案的公钥尺寸小于Maurich方案的公钥尺寸,在80比特的安全级下,改进方案的公钥从原方案的4801比特降低到240比特;在128比特的安全级下,改进方案的公钥从原方案的9857比特降低到384比特。虽然改进后的方案比原方案过程复杂,但其存储代价和计算代价变小,方案的实用性增强。