Superior High-Temperature Energy Density in Molecular Semiconductor/Polymer All-Organic Composites

High-temperature dielectric polymers are in constant demand for the multitude of high-power electronic devices employed in hybrid vehicles, grid-connected photovoltaic and wind power generation, to name a few. There is still a lack, however, of dielectric polymers that can work at high temperature (> 150 °C). Herein, a series of all-organic dielectric polymer composites have been fabricated by blending the n-type molecular semiconductor 1,4,5,8-naphthalenetetracarboxylic dianhydride (NTCDA) with polyetherimide (PEI). Electron traps are created by the introduction of trace amounts of n-type small molecule semiconductor NTCDA into PEI, which effectively reduces the leakage current and improves the breakdown strength and energy storage properties of the composite at high temperature. Especially, excellent energy storage performance is achieved in 0.5 vol.% NTCDA/PEI at the high temperatures of 150 and 200 °C, e.g., ultrahigh discharge energy density of 5.1 J cm⁻³ at 150 °C and 3.2 J cm⁻³ at 200 °C with high discharge efficiency of 85–90%, which is superior to its state-of-the-art counterparts. This study provides a facile and effective strategy for the design of high-temperature dielectric polymers for advanced electronic and electrical systems.     

Ultrathin Titanium Carbide (MXene) Films for High-Temperature Thermal Camouflage

Thermal camouflage has attracted increasing attention owing to the rapid development of infrared (IR) surveillance technologies. Various materials and systems have been developed to date, but the realization of high-temperature thermal camouflage using ultrathin film/coating remains a great challenge; this is of great significance, especially for IR stealth in military equipment. This work demonstrates a series of ultrathin Ti₃C₂T_x MXene films (as low as 1 µm) with superior high-temperature indoor/outdoor thermal camouflage performance: wide camouflage temperature range (from below −10 °C to over 500 °C), large reduction in radiation temperature (exceeding 300 °C for objects with temperatures over 500 °C), long-term high-temperature or fire stability, multifunctionality including disguised Joule heating capability, and high electromagnetic interference shielding efficiency. The superior high-temperature thermal camouflage performance of the ultrathin MXene film is attributed to its low mid-IR emissivity (0.19), which is comparable to that of stainless steel but far below that of other 2D nanomaterials, such as graphene. The multifunctional ultrathin MXene films prepared through simple vacuum-assisted filtration provide a feasible method for efficient high-temperature thermal camouflage using ultrathin films, demonstrating the great promise of MXene materials for thermal camouflage, IR stealth, counter-surveillance, and security protection.     

3D HfO2 Thin Film MEMS Capacitor with Superior Energy Storage Properties

Capacitors are ubiquitous and crucial components in modern technologies. Future microelectronic devices require novel dielectric capacitors with higher energy storage density, higher efficiency, better frequency and temperature stabilities, and compatibility with integrated circuit (IC) processes. Here, in order to overcome these challenges, a novel 3D HfO₂ thin film capacitor is designed and fabricated by an integrated microelectromechanical system (MEMS) process. The energy storage density (ESD) of the capacitor reaches 28.94 J cm⁻³, and the energy storage efficiency of the capacitor is up to 91.3% under an applied electric field of 3.5 MV cm⁻¹. The ESD can be further improved by reducing the minimum period structure size of the 3D capacitor. Moreover, the 3D capacitor exhibits excellent temperature stability (up to 150 °C) and charge-discharge endurance (10⁷ cycles). The results indicate that the 3D HfO₂ thin film MEMS capacitor has enormous potential in energy storage applications in harsh environments, such as pulsed discharge and power conditioning electronics.     

Highly reliable flip-chip-on-flex package using multilayered anisotropic conductive film

Anisotropic conductive film (ACF) has been used as interconnect material for flat-panel display module packages, such as liquid crystal displays (LCDs) in the technologies of tape automated bonding (TAB), chip-on-glass (COG), chip-on-film (COF), and chip-on-board (COB). Among them, COF is a relatively new technology after TAB and COG bonding, and its requirement for ACF becomes more stringent because of the need of high adhesion and fine-pitch interconnection. To meet these demands, strong interfacial adhesion between the ACF, substrate, and chip is a major issue. We have developed a multilayered ACF that has functional layers on both sides of a conventional ACF layer to improve the wetting properties of the resin on two-layer flex for better interface adhesion and to control the flow of conductive particles during thermocompression bonding and the resulting reliability of the interconnection using ACF. To investigate the enhancement of electrical properties and reliability of multilayered ACF in COF assemblies, we evaluated the performance in contact resistance and adhesion strength of a multilayered ACF and single-layered ACF under various environmental tests, such as a thermal cycling test (−55°C/+160°C, 1,000 cycles), a high-temperature humidity test (85°C/85% RH, 1,000 h), and a high-temperature storage test (150°C, 1,000 h). The contact resistance of the multilayered ACF joint was in an acceptable range of around a 10% increase of the initial value during the 85°C/85% RH test compared with the single-layered ACF because of the stronger moisture resistance of the multilayered ACF and flex substrate. The multilayered ACF has better adhesion properties compared with the conventional single-layered ACF during the 85°C/85% RH test because of the enhancement of the wetting to the surface of the polymide (PI) flex substrate with an adhesion-promoting nonconductive film (NCF) layer of multilayered ACF. The new ACF of the multilayered structure was successfully demonstrated in a fine-pitch COF module with a two-layer flex substrate.     

Simplification of Low-Temperature Sintering Nanosilver for Power Electronics Packaging

Conventional solders cannot meet the requirements for high-temperature applications. Recently, a low-temperature sintering technique involving a nanosilver paste has been developed for attaching semiconductor chips to substrates. Sintered nanosilver joints showed high reliability in high-temperature applications. We used the nanosilver paste to attach 10 mm × 10 mm chips by introducing a pressure as low as only 1 MPa during drying at 185°C. Die-shear tests showed that shear strengths of higher than 50 MPa could be generated by applying 5 MPa at 225°C for only 10 s or 1 MPa at 150°C for 600 s, followed by sintering for only 60 s at 275°C. The sintering temperature could be reduced to 250°C in most applications with a slight reduction in shear strength. As a result of good bonding, significant plastic flow and ductile fracture of the sheared silver joint could be observed by scanning electron microscopy (SEM). SEM also showed that the fracture of the sheared silver joint was a cohesive failure.     

Dielectric Properties and Defect Chemistry of WO3-Doped K0.5Na0.5NbO3 Ceramics

The dielectric properties and conductivity behavior of WO₃-doped K_0.5Na_0.5 NbO₃ ceramics were investigated as a function of temperature (25°C to 600°C) and frequency (40 Hz to 10⁶ Hz). The dielectric loss and direct-current (DC) conductivity of the ceramics depend strongly on the tungsten content. A high-temperature dielectric relaxation near temperature of 500°C was observed and analyzed using the semiempirical complex Cole–Cole equation. The activation energy of the dielectric relaxation was estimated to be ～2 eV and increased with increasing WO₃. The frequency-dependent conductivity can be well described by the universal dielectric response law. The activation energy obtained from the DC conductivity changes from 0.93 eV to 1.49 eV. A possible mechanism for the high-temperature dielectric relaxation and conductivity is proposed based on the activation energy value and defect compensation.     

The maximum dielectric strength of thin silicon oxide films

Thin film silicon oxide capacitors with nonshorting breakdowns were investigated. Breakdowns appear in three forms: single hole, self-propagating, and maximum voltage breakdowns. Single hole and self-propagating breakdowns occur at flaws, and self-propagating breakdowns develop only when the resistor to the source is relatively small, less than 10 kΩ in these experiments. After flaws are burned out by single hole breakdowns, with larger source resistors the maximum voltage breakdown can be observed, destroying the whole capacitor simultaneously. Plotting current against voltage, the current increase is quasi-exponential, but prior to maximum voltage breakdown, the current continues to increase while the voltage decreases slightly below a maximum value Vm. Assuming thermal instability as the cause for this change in the I-V relationship, we have derived an expression for the maximum voltage Vm. Calculated results for fields up to 9.5 MV/cm were found to agree well with measurements for temperatures from -145°C to 65°C and for thicknesses from 3000 Å to 50 000 Å. Fmdecreases with increasing temperature and thickness of insulation, and is higher for silicon dioxide than for silicon monoxide films. Maximum voltage breakdown occurs when the quasi-exponential increase of leakage current with field produces thermal instability over the whole capacitor area. The maximum dielectric strength is characteristic of the whole capacitor and is determined by its electrical and thermal conductance.     

Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory

The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO₂‐Al₂O₃‐ZrO₂/TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO₃, which has a dielectric constant of >100, even at a thickness ～10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO₂ and Al‐doped TiO₂ films might find space to fill the gap between ZAZ and SrTiO₃ MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO₂‐based dielectrics, which depends on having a dense, uniform and smooth RuO₂ layer as bottom electrode. Although the Ru (and RuO₂) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO₄ precursor made a thin, uniform, and denser Ru and RuO₂ layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO₃ films, grown at 370 °C, was ～150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO₃ film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.     

Thin gate and analog capacitor dielectrics for submicron device fabrication

The miniaturization of devices in ULSI circuits are accompanied by shrinking vertical, as well as horizontal, device parameters such as junction depth, lateral impurity diffusion and film thicknesses. This is achieved by decoupling process steps,i.e. processing at a reduced thermal budget. However, as device dimensions decrease, greater demand in transistor noise immunity and reliability may not be achievable with low-temperature (<900° C) oxidation processes. Low temperature CVD ONO (oxide-nitride-oxide) dielectrics have been evaluated for applications in ULSI gate as well as capacitor structures. Time dependent dielectric breakdown data have shown that ONO has longer lifetime than thermal oxide of equivalent thickness. Such stacked dielectrics nevertheless result in complex processing steps. With the advances in rapid thermal processing equipment today, rapid thermal oxide (RTO) has been shown to offer potential benefits of high temperature without significant addition to the overall thermal budget. We have shown that transistors with RTO gate oxides exhibit longer lifetime and lower noise compared to those with furnace grown gate oxides. We have also shown that interpoly RTO oxides have remarkable dielectric strength of >8 MV/cm. For enhanced radiation hardness and impurity masking capability as well as higher permittivity, rapid thermal nitrided oxides may be a potential choice deserving further evaluation. These nitrided oxides must be reoxidized to reduce densities of interface states and electron traps created during the nitridation process.     

High-Temperature Capacitor Materials Based on Modified BaTiO<Subscript>3</Subscript>

High-temperature capacitor materials sintered at 1120°C were prepared in a BaTiO₃ (BT)-Na_0.5Bi_0.5TiO₃ (NBT)-Nb₂O₅-ZnO-CaZrO₃ system. The Curie temperature of BaTiO₃ was increased by NBT doping, and a secondary phase occurred when adding ≥5 mol% NBT. The effects of Nb₂O₅, ZnO, and CaZrO₃ on the dielectric properties and the microstructure of BT ceramics doped with 1 mol% NBT were analyzed. The overall dielectric constant decreased when the Nb₂O₅ content increased, and increased when the ZnO content increased. The dielectric constant peak at the Curie temperature was effectively depressed, and a broad secondary dielectric constant peak appeared at 60°C when the ZnO concentration was ≥4.5 mol%. Significant grain growth was observed by scanning electron microscope (SEM) analysis as the amount of ZnO increased. The high-temperature capacitor specification (−55°C to +175°C, ΔC/C _25°C less than ±15%) is met when 7 mol% to 8 mol% CaZrO₃ is added.     

Good Thermal Stability,High Permittivity,Low Dielectric Loss and Chemical Compatibility with Silver Electrodes of Low-Fired BaTiO<Subscript>3</Subscript>–Bi(Cu<Subscript>0.75</Subscript>W<Subscript>0.25</Subscript>)O<Subscript>3</Subscript> Ceramics

(1 ? x)BaTiO₃–xBi(Cu_0.75W_0.25)O₃ [(1 ? x)BT–xBCW, 0 ≤ x ≤ 0.04] perovskite solid solutions ceramics of an X8R-type multilayer ceramic capacitor with a low sintering temperature (900°C) were synthesized by a conventional solid state reaction technique. Raman spectra and x-ray diffraction analysis demonstrated that a systematically structural evolution from a tetragonal phase to a pseudo-cubic phase appeared near 0.03 < x < 0.04. X-ray photoelectron analysis confirmed the existence of Cu⁺/Cu²⁺ mixed-valent structure in 0.96BT–0.04BCW ceramics. 0.96BT–0.04BCW ceramics sintered at 900°C showed excellent temperature stability of permittivity (Δε/ε _25°C ≤ ±15%) and retained good dielectric properties (relative permittivity ～1450 and dielectric loss ≤2%) over a wide temperature range from 25°C to 150°C at 1 MHz. Especially, 0.96BT–0.04BCW dielectrics have good compatibility with silver powders. Dielectric properties and electrode compatibility suggest that the developed materials can be used in low temperature co-fired multilayer capacitor applications.     

Investigation of MOS capacitors with thin ZrO2layers and various gate materials for advanced DRAM applications

Thin ZrO2layers were used to realize MOS capacitors with aluminum, polysilicon, and molybdenum gate electrodes. The layers, 300-600 Å in thickness, were obtained by metal organic chemical vapor deposition. The effects of various high-temperature treatments as well as gate material deposition conditions on the MOS capacitor properties were studied. Processing conditions compatible with standard silicon technology were established to obtain capacitors suitable for advanced DRAM application. Relative dielectric constant ∈ ≥ 16, breakdown fieldE_{B} ge 3MV/cm, and leakage currents at applied voltage of 5V around 10^-8A/cm²enable the realization of capacitors with dielectric layer equivalent to 35 Å of SiO2.     

A Facile In Situ Surface-Functionalization Approach to Scalable Laminated High-Temperature Polymer Dielectrics with Ultrahigh Capacitive Performance

High-temperature dielectric materials for capacitive energy storage are in urgent demand for modern power electronic and electrical systems. However, the drastically degraded energy storage capabilities owing to the inevitable conduction loss severely limit the utility of dielectric polymers at elevated temperatures. Herein, a new approach based on the in situ preparation of oxides onto polyimide (PI) films to high-temperature laminated polymer dielectrics is described. As confirmed by computational simulations, the charge injection at the electrode/dielectric interface and electrical conduction in dielectric films are substantially depressed via engineering the in situ prepared oxide layer in the laminated composites. Consequently, ultrahigh dielectric energy densities and high efficiencies are simultaneously achieved at elevated temperatures. Especially, an excellent energy density of 1.59 J cm⁻³ at a charge–discharge efficiency of above 90% has been achieved at 200 °C, outperforming the current dielectric polymers and composites. Together with its excellent discharging capability and cyclic reliability, the laminate-structured film is demonstrated to be a promising class of polymer dielectrics for high-power energy storage capacitors operating at elevated temperatures. The facile preparation method reported herein is readily adaptable to a variety of polymer thin films for energy applications under extreme environments.     

A Novel Electroless Process for Embedding a Thin Film Resistor on the Benzocyclobutene Dielectric

To realize embedded resistors on multilayer benzocyclobutene (BCB) either on-chip or on-board, a low-cost large format electroless process for deposition of NiP and NiWP thin-film resistors using both low-temperature (25°C) and high-temperature (90°C) baths has been developed. The electroless process exhibits uniform resistor thickness in the submicron range and offers low profile and excellent adhesion to the BCB dielectric layer. The resistor films also act as a seed layer for direct electroplating of copper traces. The NiP alloys can also be tailored to a variable temperature coefficient of resistance (TCR) with different alloy compositions. The electroless process can be adopted in the PCB manufacturing industries with no additional investment. This article is the first report on electroless plated thin film resistors on low loss BCB dielectric.     

MEMS高温压力传感器耐高温引线结构优化

绝缘体上硅(SOI)高温压力传感器可在高温(高于125 ℃)下工作。通常情况下构成惠斯通电桥的电阻单独处于压力敏感区,以提高其灵敏度,但在其工作期间压力传感器器件区电阻重掺区与金属引线连接处存在一定高度差,在加压加电高温环境下此处热应力变大,金属引线因过热而出现金属引线断裂或失效,无法满足高温需求。在此基础上研究了一种硅引线技术,使其与压敏电阻处于同一高度层,金属引线平铺在硅引线上端,经退火后形成良好的欧姆接触。实验测试表明,该方案能使压力传感器在300 ℃高温环境下正常工作,金属引线与电阻区连接完好,传感器敏感区应力降低接近50%,且优化后传感器灵敏度符合设计要求。     

Scalable,Versatile Synthesis of Ultrathin Polyetherimide Films and Coatings via Interfacial Polymerization

Polyetherimides (PEI) are high-performance thermoplastic polymers featuring a high dielectric constant and excellent thermal stability. In particular, PEI thin films are of increasing interest for use in solid-state capacitors and membranes, yet the cost and thickness are limited by conventional synthesis and thermal drawing techniques. Here, a method of synthesizing ultrathin PEI films and coatings is introduced based on interfacial polymerization (IP) of poly(amic acid), followed by thermal imidization. Control of transport, reaction, and precipitation kinetics enables tailoring of PEI film morphology from a nanometer-scale smooth film to a porous micrometer-scale layer of polymer microparticles. At short reaction times (≈1 min) freestanding films are formed with ≈1 µm thickness, which to our knowledge surpass commercial state-of-the-art films (3–5 µm minimum thickness) made by thermal drawing. PEI films synthesized via the IP route have thermal and optical properties on par with conventional PEI. The use of the final PEI is demonstrated in structurally colored films, dielectric layers in capacitors, and show that the IP route can form nanometer-scale coatings on carbon nanotubes. The rapid film formation rate and fine property control are attractive for scale-up, and established methods for roll-to-roll processing can be applied in future work.     

New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO₂ and amorphous phase Al₂O₃ in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Å and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.     

A study on the temperature dependence of epoxy/BaTiO<Subscript>3</Subscript> composite embedded capacitor films

In this study, the temperature dependence of capacitance, one of the most important properties of embedded capacitor films (ECFs), was investigated. The temperature dependence of the capacitance of ECFs was determined by the temperature dependence of the dielectric constant and thickness, and among these, the main factor was the dielectric constant of ECFs. The dielectric constant of ECFs was determined by that of epoxy and BaTiO₃ powders. Below 130°C, the dielectric constant of ECFs increased as temperature increased, and was mainly affected by an epoxy matrix. However, above 130°C (the Curie temperature of BaTiO₃), the increased rate of the dielectric constant of ECFs started decreasing. This was due to the fact that BaTiO₃ powder undergoes a phase transition from a tetragonal to a cubic structure, and its dielectric constant decreases at 130°C. The dielectric constant of BaTiO₃ powder was obtained from measured dielectric constants of ECF and application of the Lichtenecker logarithmic rule.     

High-Energy-Density Poly(styrene-co-acrylonitrile) Thin Films

The dielectric response of poly(styrene-co-acrylonitrile) (PSAN) thin films fabricated by a solution casting process was investigated in this work. Linear dielectric behavior was obtained in PSAN films under an electric field at frequencies from 100 Hz to 1 MHz and temperature of ?50°C to 100°C. The polymer films exhibited an intermediate dielectric permittivity of 4 and low dielectric loss (tan δ) of 0.027. Under 400 MV/m, the energy density of the PSAN films was 6.8 J/cm³, which is three times higher than that of biaxially oriented polypropylene (BOPP) (about 1.6 J/cm³). However, their charge–discharge efficiency (about 90%) was rather close to that of BOPP. The calculated effective dielectric permittivity of the PSAN films under high electric field was as high as 9, which may be attributed to the improved displacement of the cyanide groups (–CN) polarized at high electric fields. These high-performance features make PSAN attractive for high-energy-density capacitor applications.     

SiC field-effect devices operating at high temperature

Field-effect devices based on SiC metal-oxide-semiconductor (MOS) structures are attractive for electronic and sensing applications above 250°C. The MOS device operation in chemically corrosive, high-temperature environments places stringent demands on the stability of the insulating dielectric and the constituent interfaces within the structure. The primary mode of oxide breakdown under these conditions is attributed to electron injection from the substrate. The reliability of n-type SiC MOS devices was investigated by monitoring the gate-leakage current as a function of temperature. We find current densities below 17 nA/cm² and 3 nA/cm² at electric field strengths up to 0.6 MV/cm and temperatures of 330°C and 180°C, respectively. These are promising results for high-temperature operation, because the optimum bias point for SiC MOS gas sensors in near midgap, where the field across the oxide is small. Our results are valid for n-type SiC MOS sensors in general and have been observed in both the 4H and 6H polytypes.