Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni₃P and (Cu,Ni)₆Sn₅ after thermal aging, while the substrate pad region contains Cu₃Sn and (Cu,Ni)₆Sn₅. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)₆Sn₅ on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm²/h, 0.1423 μm²/h, and 0.4463 μm²/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.     

Highly reliable, fine pitch chip on glass (COG) joints fabricated using Sn/Cu bumps and non-conductive adhesives

We have developed a reliable and ultra-fine pitch chip on glass (COG) bonding technique using Sn/Cu bumps and non-conductive adhesive (NCA). Sn/Cu bumps were formed by electroplating and reflowed, forming dome shaped Sn bumps on Cu columns. COG bonding was performed between the reflowed Sn/Cu bumps on the oxidized Si wafer and ITO/Au/Cu/Ti/glass substrate using a thermo-compression bonder. Three different NCAs were applied during bonding. Bonding temperature was 150 °C for NCA-A and NCA-B, and 110 °C for NCA-C. The electrical properties of COG joints were evaluated by measuring the contact resistance of each joint through the four-point probe method. All joints were successfully bonded and the electrical measurement showed that the average contact resistance of each joint was approximately 30 mΩ, regardless of NCA types. The COG joints were subjected to a series of reliability tests: high temperature storage test (85 °C, 160 h); thermal cycling test (−40 °C/+85 °C, 20 cycle); and a temperature and humidity test (50 °C/90%, 160 h) were sequentially performed to evaluate the reliability of the COG joints. The contact resistance measurement showed that there were no failed bumps in all specimens and all joints passed the criterion after reliability test.     

Thermoelectric Power Generation Characteristics of a Thin-Film Device Consisting of Electrodeposited n-Bi2Te3 and p-Sb2Te3 Thin-Film Legs

A thermoelectric thin-film device of the cross-plane configuration was fabricated by flip-chip bonding of the top electrodes to 242 pairs of electrodeposited n-type Bi₂Te₃ and p-type Sb₂Te₃ thin-film legs on the bottom substrate. The electrodeposited Bi₂Te₃ and Sb₂Te₃ films of 20-μm thickness exhibited Seebeck coefficients of ?59 μV/K and 485 μV/K, respectively. The internal resistance of the thin-film device was measured as 3.7 kΩ, most of which was attributed to the interfacial resistance of the flip-chip joints. The actual temperature difference ΔT _G working across the thin-film legs was estimated to be 10.4 times smaller than the apparent temperature difference ΔT applied across the thin-film device. The thin-film device exhibited an open-circuit voltage of 0.294 V and a maximum output power of 5.9 μW at an apparent temperature difference ΔT of 22.3 K applied across the thin-film device.     

Intermetallic Compound Growth and Reliability of Cu Pillar Bumps Under Current Stressing

Fine-pitch Cu pillar bumps have been adopted for flip-chip bonding technology. Intermetallic compound (IMC) growth in Cu pillar bumps was investigated as a function of annealing or current stressing by in situ observation. The effect of IMC growth on the mechanical reliability of the Cu pillar bumps was also investigated. It is noteworthy that Sn exhaustion was observed after 240 h of annealing when current stressing was not applied, and IMC growth rates were changed remarkably. As the applied current densities increased, the time required for complete Sn consumption became shorter. In addition, Kirkendall voids, which would be detrimental to the mechanical reliability of Cu pillar bumps, were observed in both Cu₃Sn/Cu pillars and Cu₃Sn/Cu under-bump metallization interfaces. Die shear force was measured for Cu pillar samples prepared with various annealing times, and degradation of mechanical strength was observed.     

Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S₂₁ parameter was measured up to 20 GHz.     

Influence of crystallographic orientation of Sn-Ag-Cu on electromigration in flip-chip joint

The influence of the crystallographic orientation of Sn-3.0 wt%Ag-0.5 wt%Cu flip-chip joints and underfill on electromigration was investigated. The current density applied in our tests was 15 kA/cm² at 160 °C. Various times to failure of the test samples show a clear dependence of the electromigration behavior on the Sn grain orientations. Different microstructural evolutions were observed in all solder bumps in correlation with the crystallographic orientations of the Sn grains after an electromigration test. The primary failure of the solder joints was caused by dissolution of the Cu electrode at the cathode interface. Rapid dissolution of the Cu electrode occurred when the c-axis of the Sn grains was parallel to the direction of electron flow. On the other hand, slight dissolution of the Cu electrode was observed when the c-axis of the Sn grains was perpendicular to the direction of electron flow. Some grain boundaries interrupt the migration of Cu and the trapped Cu atoms form new grains of intermetallic compounds at the grain boundaries. In addition, underfill inhibits serious deformation of solder bumps during current stressing.     

Relieving Hot-Spot Temperature and Current Crowding Effects During Electromigration in Solder Bumps by Using Cu Columns

Solder joints with Cu columns appear to be one of the best structures to resist electromigration. Three-dimensional thermoelectrical analysis was employed to simulate the current density and temperature distributions for eutectic SnPb solder bumps with 0.5, 5, 25, 50, and 100 μm Cu under bump metallization (UBM). It was found that the hot spots and current crowding effects in the solder were reduced significantly when the Cu thickness was over 50 μm, whereas the overall Joule heating effect remained almost unchanged. The mechanism by which the Cu column is effective in relieving the hot spot and current crowding effects is to keep the solder away from the heat source and crowding region. Simulated at a current of 0.6 A and 70°C, the estimated mean time to failure of the joints with a 50-μm-thick Cu column was 6.7 times longer than that of joints with a 0.5-μm-thick Cu UBM.     

A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

The Cu/SnAg double-bump structure is a promising candidate for fine-pitch flip-chip applications. In this study, the interfacial reactions of Cu (60 μm)/SnAg (20 μm) double-bump flip chip assemblies with a 100 μm pitch were investigated. Two types of thermal treatments, multiple reflows and thermal aging, were performed to evaluate the thermal reliability of Cu/SnAg flip-chip assemblies on organic printed circuit boards (PCBs). After these thermal treatments, the resulting intermetallic compounds (IMCs) were identified with scanning electron microscopy (SEM), and the contact resistance was measured using a daisy-chain and a four-point Kelvin structure. Several types of intermetallic compounds form at the Cu column/SnAg solder interface and the SnAg solder/Ni pad interface. In the case of flip-chip samples reflowed at 250°C and 280°C, Cu₆Sn₅ and (Cu, Ni)₆Sn₅ IMCs were found at the Cu/SnAg and SnAg/Ni interfaces, respectively. In addition, an abnormal Ag₃Sn phase was detected inside the SnAg solder. However, no changes were found in the electrical contact resistance in spite of severe IMC formation in the SnAg solder after five reflows. In thermally aged flip-chip samples, Cu₆Sn₅ and Cu₃Sn IMCs were found at the Cu/SnAg interface, and (Cu, Ni)₆Sn₅ IMCs were found at the SnAg/Ni interface. However, Ag₃Sn IMCs were not observed, even for longer aging times and higher temperatures. The growth of Cu₃Sn IMCs at the Cu/SnAg interface was found to lead to the formation of Kirkendall voids inside the Cu₃Sn IMCs and linked voids within the Cu₃Sn/Cu column interfaces. These voids became more evident when the aging time and temperature increased. The contact resistance was found to be nearly unchanged after 2000 h at 125°C, but increases slightly at 150°C, and a number of Cu/SnAg joints failed after 2000 h. This failure was caused by a reduction in the contact area due to the formation of Kirkendall and linked voids at the Cu column/Cu₃Sn IMC interface.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Electromigration Reliability and Morphologies of Cu Pillar Flip-Chip Solder Joints with Cu Substrate Pad Metallization

The Cu pillar is a thick underbump metallurgy (UBM) structure developed to alleviate current crowding in a flip-chip solder joint under operating conditions. We present in this work an examination of the electromigration reliability and morphologies of Cu pillar flip-chip solder joints formed by joining Ti/Cu/Ni UBM with largely elongated ∼62 μm Cu onto Cu substrate pad metallization using the Sn-3Ag-0.5Cu solder alloy. Three test conditions that controlled average current densities in solder joints and ambient temperatures were considered: 10 kA/cm² at 150°C, 10 kA/cm² at 160°C, and 15 kA/cm² at 125°C. Electromigration reliability of this particular solder joint turns out to be greatly enhanced compared to a conventional solder joint with a thin-film-stack UBM. Cross-sectional examinations of solder joints upon failure indicate that cracks formed in (Cu,Ni)₆Sn₅ or Cu₆Sn₅ intermetallic compounds (IMCs) near the cathode side of the solder joint. Moreover, the ~52-μm-thick Sn-Ag-Cu solder after long-term current stressing has turned into a combination of ~80% Cu-Ni-Sn IMC and ~20% Sn-rich phases, which appeared in the form of large aggregates that in general were distributed on the cathode side of the solder joint.     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

Three-Dimensional Thermoelectrical Simulation in Flip-Chip Solder Joints with Thick Underbump Metallizations during Accelerated Electromigration Testing

In flip-chip solder joints, thick Cu and Ni films have been used as under bump metallization (UBM) for Pb-free solders. In addition, electromigration has become a crucial reliability concern for fine-pitch flip-chip solder joints. In this paper, the three-dimensional (3-D) finite element method was employed to simulate the current-density and temperature distributions for the eutectic SnPb solder joints with 5-μm Cu, 10-μm Cu, 25-μm Cu, and 25-μm Ni UBMs. It was found that the thicker the UBM is the lower the maximum current density inside the solder. The maximum current density is 4.37 × 10⁴ A/cm², 1.69 × 10⁴ A/cm², 7.54 × 10³ A/cm², and 1.34 × 10⁴ A/cm², respectively, when the solder joints with the above four UBMs are stressed by 0.567 A. The solder joints with thick UBMs can effectively relieve the current crowding effect inside the solder. In addition, the joint with the thicker Cu UBM has a lower Joule heating effect in the solder. The joint with the 25-μm Ni UBM has the highest Joule heating effect among the four models.     

Ultrafine-Grain and Isotropic Cu/SAC305/Cu Solder Interconnects Fabricated by High-Intensity Ultrasound-Assisted Solidification

With the miniaturization of portable electronic devices, the size of solder joint interconnects is decreasing to micrometer levels. These joints possess only several or even one or two grains, resulting in anisotropy and failure issues. Direct ultrasound-assisted solidification of Cu/SAC305/Cu interconnects for grain refinement and fabrication of isotropic solder joints is presented herein. These joints consist of many β-Sn grains. The average cross-sectional area of the Sn-rich phase is significantly reduced by up to 99% when compared with conventional as-reflowed samples. The ultrasonic power density exhibits a threshold value for affecting the microstructures. Below 200 W cm^?2, the β-Sn grains were refined and had circular shape. The Ag₃Sn phase grew in a manner similar to branched coral to sizes reaching 30 μm, or as rods aggregated together with Cu₆Sn₅ tube fragments. Above 200 W cm^?2, the microstructures were coarsened and Ag₃Sn had plate-like shape. The thickness of Cu₆Sn₅ intermetallic layers at the Cu/solder interfaces was reduced by more than 26%. The relationships among the ultrasonic power, nucleation rate, local temperature drop, and pressure were identified. At the highest power density of 267 W cm^?2, the nucleation rate was about 4.05 × 10¹⁴ m^?3 s^?1, the local temperature drop was 248 K, and the local pressure was on the order of several GPa.     

Cadmium Telluride Solar Cells on Ultrathin Glass for Space Applications

This paper details the preliminary findings of a study to achieve a durable thin-film CdTe photovoltaic (PV) device structure on ultrathin space-qualified cover glass. An aluminum-doped zinc oxide (AZO) transparent conducting oxide was deposited directly onto the cover glass using metalorganic chemical vapor deposition (MOCVD). The AZO demonstrated low sheet resistance of 10 Ω/□ and high optical transparency of 85% as well as excellent adherence and environmental stability. Preliminary deposition of PV layers onto the AZO on cover glass, by MOCVD, showed the possibility of such a structure, yielding a device conversion efficiency of 7.2%. High series resistance (10 Ω cm²) and low V _oc (586 mV) were identified as the limiting factors when compared with the authors’ platform process on indium tin oxide-coated aluminosilicate. The coverage of the Cd_1?x Zn _x S window layer along with the front contacting of the device were shown to be the major causes of the low efficiency. Further deposition of AZO/CdTe employing an oxygen plasma cleaning step to the cover glass and evaporated gold front contacts significantly improved the device performance. With a highest conversion efficiency of 10.2%, series resistance improved to 4.4 Ω cm², open-circuit voltage (V _oc) up to 667 mV, and good adhesion, this represents the first demonstration of direct deposition of CdTe solar cells onto 100-μm-thick space-qualified cover glass.     

Sn whisker evaluations in 3D microbumped structures

Sn whiskering remains a reliability concern in electronic applications. Despite extensive research on growth rates and mitigation strategies, no predictive theory is in place. Literature data are available for Cu/Sn-based films and coatings as well as for board-level and flip-chip solder bumps but data are scarce for scaled-down solder volumes and for higher intermetallic-to-solder ratios. The current work investigates whiskers in “isolated geometries” for 3D solder-capped Cu microbumps with >2 orders of magnitude smaller solder volumes compared to state-of-the-art. To the best of the authors’ knowledge, this is the first time Sn whisker growth is reported in isolated solder volumes (e.g. <8 μm-side cube). Whiskers propensity was evaluated using JEDEC industrial specifications. The tested structures were: 5/3.5 μm-thick Cu/Sn films and 15 μm-diameter electroplated solder capping (Sn, SnAg, SnCu) on Cu microbumps (as-plated vs. reflowed). Selected Sn whiskers and “whisker-like” features were analysed and identified experimentally with SEM, EDX and FIB. In the absence of a predictive model, first-order and “what if” calculations based on IMC molar volume and oxide cracking hypotheses were carried out. This approach quantifies “figures of merit” for Sn whisker propensity with (1) different bump-limiting metallization (BLM) cases e.g. Cu, Ni, Co and (2) further microbump scaling. Future research recommendations are outlined to mitigate manufacturing risks by controlling “sit time” between bumping and stacking.     

Chip to Chip Bonding Using Cu Bumps Capped with Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints

Chip to chip bonding techniques using Cu bumps capped with thin solder layers have been frequently applied to 3D chip stacking technology. We studied the effect of joint microstructure on shear strength. Joints were formed by joining Sn/Cu bumps on a Si die and Sn/Cu layers on another Si die at 245–330°C using a thermo-compression bonder. Three different types of microstructures were fabricated in the joints by controlling the bonding temperature and time, (1) a Sn-rich phase with a Cu₆Sn₅ phase at the Cu interfaces, (2) a Cu₆Sn₅ phase in the interior with a Cu₃Sn phase at the Cu interfaces, and (3) one single Cu₃Sn phase throughout the whole joint. The joint having a single Cu₃Sn phase had the highest shear strength. Specimens were aged up to 2000 h at 150°C and 180°C. During aging, the microstructures of all joints were transformed in a single Cu₃Sn phase. The shear strength of the joints was very sensitive to the formation of Cu₃Sn and microvoids. Microvoids formed in the solder joints with a Cu₆Sn₅ phase with and without a Sn-rich phase during aging and decreased the shear strength of the joints. Conversely, aging did not induce the formation of microvoids in the joints which originally had only a Cu₃Sn phase and the shear strength was not decreased.     

EBSD Investigation of Cu-Sn IMC Microstructural Evolution in Cu/Sn-Ag/Cu Microbumps During Isothermal Annealing

The microstructural evolution of Cu/Sn-Ag (~5 μm)/Cu Cu-bump-on-line (CuBOL) joints during isothermal annealing at 180°C was examined using a field-emission scanning electron microscope equipped with an electron backscatter diffraction (EBSD) system. Cu₆Sn₅ and Cu₃Sn were the two key intermetallic compound (IMC) species that appeared in the CuBOL joints. After annealing for 24 h (= t), the solder had completely converted to Cu-Sn IMCs, forming an “IMC” joint with Cu/Cu₃Sn/Cu₆Sn₅/Cu₃Sn/Cu structure. EBSD analyses indicated that the preferred orientation of the hexagonal Cu₆Sn₅ (η) was $ (2\bar{1}\bar{1}3) $ , while the preferred orientation was (100) for the monoclinic Cu₆Sn₅ structure (η′). Upon increasing t to 72 h, Cu₆Sn₅ entirely transformed into Cu₃Sn, and the IMC joint became Cu/Cu₃Sn/Cu accordingly. Interestingly, the grain size and crystallographic orientation of Cu₃Sn displayed location dependence. Detailed EBSD analyses in combination with transmission electron microscopy on Cu₃Sn were performed in the present study. This research offers better understanding of crystallographic details, including crystal structure, grain size, and orientation, for Cu₆Sn₅ and Cu₃Sn in CuBOL joints after various annealing times.     

Cu2ZnSnSe4 Solar Cells with Absorbers Prepared by the Metallic Ink-Printing Method Using Nanosized Cu-Zn-Sn Pastes and Selenization

A large-grained Cu₂ZnSnSe₄ (CZTSe) absorber for solar cells was fabricated by the metallic ink-printing method and subsequent selenization at 600°C to 700°C with overpressures of two different selenium compounds and a step-heating procedure. The developed CZTSe grain size was confirmed as 8 μm to 20 μm. The second heating stage was helpful in inducing crystallization and was important for grain growth. For the nonvacuum approach, nanosized Cu, Zn, and Sn powders were chosen for preparing inks. Ceramic Al₂O₃ was used instead of glass to prevent the thermal decomposition of the substrate. A nanosized Cu(In,Ga)Se₂ layer was coated on a Mo electrode to provide a barrier to avoid direct contact of Cu, Zn, and Sn with Mo. The selenization under the combination of two selenide pellets played a crucial role in preparing the CZTSe absorber. The fabricated CZTSe solar cell device showed power conversion efficiency of 1.14%, open-circuit voltage of 130 mV, short-circuit current density of 33.1 mA/cm², and fill factor of 0.265.     

Effect of polyimide baking on bump resistance in flip-chip solder joints

The effect of polyimide (PI) thermal process on the bump resistance of flip-chip solder joint is investigated for 28 nm technology device with aggressive extreme low-k (ELK) dielectric film scheme and lead-free solder. Kelvin structure is designed in the bump array to measure the resistance of single solder bump. An additional low-temperature pre-baking before standard PI curing increases the bump resistance from 9.3 mΩ to 225 mΩ. The bump resistance increment is well explained by a PI outgassing model established based on the results of Gas Chromatography–Mass Spectrophotometer (GC–MS) analysis. The PI outgassing substances re-deposit on the Al bump pad, increasing the resistance of interface between under-bump metallurgy (UBM) and underneath Al pad. The resistance of interface is twenty-times higher than pure solder bump, which dominates the measured value of bump resistance. Low-temperature plasma etching prior to UBM deposition is proposed to retard the PI outgassing, and it effectively reduces the bump resistance from 225 mΩ to 10.8 mΩ.