Performance of Parallel Concatenated Coding Schemes

In this paper, ensembles of parallel concatenated codes are studied and rigorous results on their asymptotic performance, under the assumption of maximum-likelihood (ML) decoding, are presented. In particular, it is proven that in any parallel concatenation scheme with k branches where all k encoders are recursive and the Bhattacharyya parameter of the channel is sufficiently small, the bit-error rate (BER) and the word-error rate go to 0 exactly like N ^1- k and N ^2- k, respectively. Different types of ensembles by changing the subgroup of permutations used to interconnect the various encoders, are considered.     

级联卷积码的性能评估

本文给出了三个采用卷积码的数字通信系统,并对其性能进行了评估.其中两个系统采用了用两个短的卷积码进行级联的方式(称为级联系统). 而另一个则是现在普遍使用的卷积编码方式,它采用一个长的卷积码(称为基联系统),三个系统的编码效率和约束长度分别采用R=2/3和K=3,R=3/4和K=2,以及R=1/2和K=7.前两个系统在Viterbi译码器进行硬件判决之前采用了软判决.两个级联系统中最为突出的特点是它们的译码器的复杂程度被大大降低,整个系统的复杂程度比基联系统改变了25%到50%.     

并行级联卷积码的最新进展

并行级联卷积码（Ｔｕｒｂｏ码）是近年来在编码理论上的一个重大突破，其性能与信道容量极限的差距可小于１ｄＢ。有着极其广阔的应用前景。这种编码方式的优异性能来源于其独特的码结构和迭代译码算法，使其成为一种接近随机编码的可译码。它的编译思想将对编码研究产生重要影响。本文将在编码结构，性能分析与码设计、简化算法及应用等方面对这种码的研究现状与前景作一综述。     

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

This tutorial paper gives an overview of the implementation aspects related to turbo decoders, where the term turbo generally refers to iterative decoders intended for parallel concatenated convolutional codes as well as for serial concatenated convolutional codes. We start by considering the general structure of iterative decoders and the main features of the soft-input soft-output algorithm that forms the heart of iterative decoders. Then, we show that very efficient parallel architectures are available for all types of turbo decoders allowing high-speed implementations. Other implementation aspects like quantization issues and stopping rules used in conjunction with buffering for increasing throughput are considered. Finally, we perform an evaluation of the complexities of the turbo decoders as a function of the main parameters of the code.     

A New Concatenated Coding SystemUsing Multilevel Inner Codes

ＡＮｅｗＣｏｎｃａｔｅｎａｔｅｄＣｏｄｉｎｇＳｙｓｔｅｍＵｓｉｎｇＭｕｌｔｉｌｅｖｅｌＩｎｎｅｒＣｏｄｅｓＷａｎｇＤｕａｎｙｉＡＮＤＹｕｅＧｕａｎｇｘｉｎ（ＤｅｐａｒｔｍｅｎｔｏｆＴｅｌｅｃｏｍｍｕｎｉｃａｔｉｏｎＥｎｇｉｎｅｅｒｉｎｇ，Ｂｅｉｊｉｎ...     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

An Upper Bound on the Minimum Distance of Serially Concatenated Convolutional Codes

This correspondence presents an upper bound on the minimum distance of serially concatenated codes with interleaver where the inner code is a systematic recursive convolutional encoder and the outer code is any convolutional encoder. The resulting expression shows that the minimum distance of the concatenated code cannot grow more than O(K¹-1/d_f ^(O)), where K is the information word length, and d_f ^(O) is the free distance of the outer code. The obtained upper bound is shown to agree with and, in some cases, improve over previously known results     

串行级联空时码的设计

该文设计了一类适用于串行级联空时码(Serially Concatenated Space-Time Code, SCSTC)的两天线卷积空时码(Convolutional Space-Time Code, CSTC),并将该设计方法推广到多天线的情况,使SCSTC的信息速率可随天线数增加而增加;将EXIT Chart的概念推广到多天线SCSTC中,在此基础上分析了所设计SCSTC的收敛特性。与现有的SCSTC相比,该文设计的SCSTC具有更快的收敛速度和更好的抗衰落性能。     

Concatenated Coding Systems Employing a Unit-Memory Convolutional Code and a Byte-Oriented Decoding Algorithm

Concatenated coding systems utilizing a convolutional code as the inner code and a Reed-Solomon code as the outer code are considered. In order to obtain very reliable communications over a very noisy channel with relatively modest coding complexity, it is proposed to concatenate a byte-oriented unit-memory convolutional code with an RS outer code whose symbol size is one byte. It is further proposed to utilize a real-time minimal-byte-error probability decoding algorithm, together with feedback from the outer decoder, in the decoder for the inner convolutional code. The performance of the proposed concatenated coding system is studied, and the improvement over conventional concatenated systems due to each additional feature is isolated.     

A Comparison of Block and Convolutional Codes in ARQ Error Control Schemes

ARQ methods of error control can considerably improve the reliablity of data transmission in such areas as satellite communications, computer networks, etc. A number of ARQ schemes using both block and convolutional codes have appeared in the literature. In this paper, the following problem is addressed. Given two different implementations of an ARQ scheme, one using a block code and the other using a convolutional code, such that the bit error probability of both implementations does not exceed some specific value, which implementation has the higher throughput and under what conditions will it be attained? The comparison is made for three basic retransmission schemes using both hybrid and pure ARQ: stop-and-wait, go-back-N, and selective repeat. Numerical estimates of the throughput were obtained using approximate theoretical expressions for BCH codes and simulation results for sequential decoding of rate 1/2 convolutional codes. Parameters optimizing the performance of both block and convolutional codes for different channel conditions and round trip delays were found and were used to obtain these numerical estimates. Comparison of the quantitative results indicates a trend toward preferring convolutional codes as delay and/or block length increases. A binary symmetric channel with noiseless feedback was assumed. Possible implications for the Gaussian channel are also discussed.     

非二进制Turbo级联码的性能分析

该文在分析了非二进制Turbo码的译码算法的基础上,提出了非二进制Turbo码和具有良好纠突发错误的RS码级联的非二进制Turbo级联码系统模型。该系统采用缩短的RS码(204, 188)作为外码,非二进制Turbo码作为内码的串行级联方式,内码和外码之间用深度为12的交织器隔开,译码时, 非二进制Turbo码分别采用Symbol-by-Symbol Log-MAP和SOVA算法。仿真结果显示,与二进制Turbo级联码系统相比,该系统具有误码率低,延时时间短,频带利用率高等优点。     

串行级联卷积码在AWGN信道上的性能分析

文中对串行级联卷积编码（Serial Concatenated Convolutional Code,SCCC）的原理和结构进行了详细的分析,并对其在低信噪比条件下通过AWGN信道时的纠错能力进行了仿真研究。仿真结果表明,在相同信噪比的情况下,交织器的交织长度和接收端译码算法的迭代次数都对系统误码率有很大影响,并给出了合适的交织长度和迭代次数,从而以较小的代价获得更好的译码性能。     

倒谱与相位模糊条件下的卷积码高容错识别

针对倒谱、相位模糊及误码存在条件下的不同码率卷积码识别问题，本文提出了一种容错能力较强的识别算法。以(133,171)卷积码为例，在QPSK调制方式下，首先推导出符号信息到比特软信息的转换关系，然后利用本文提出的校验向量求解算法得到各个条件下的校验向量，最后利用Walsh-Hadamard变换(WHT)、对数似然比(LLR)、似然差(LD)三种方法对校验向量的识别性能进行了测试。仿真结果表明，对于(133,171)卷积码，利用求得的校验向量能够在较低信噪比下有效识别各种码率、相位模糊以及倒谱，且将分析范围从56种情况减少至2种或4种情况，计算复杂度较低，能够适应实际环境需求。      

Reliability and Throughput Analysis of a Concatenated Coding Scheme

In this paper, the performance of a concatenated coding scheme for error control in ARQ systems is analyzed for both randomerror and burst-error channels. In particular, the probability of undetected error and the system throughput are calculated. In this scheme, the inner code is used for both error correction and error detection, and the outer code is used for error detection only. Interleaving/deinterleaving of the outer code is assumed. A retransmission is requested if either the inner code or the outer code detects the Presence of errors. Various coding examples are considered. The results show that concatenated coding can provide extremely high system reliability (i.e., low probability of undetected error) and high system throughput.     

一种应用于DMB-T的基于RS码软判决译码的级联码方案

结合DMB—T系统的信道编码方案以及编码领域的最新进展,即RS码软判决译码算法的发展,提出了一种应用于DMB-T系统基于和积算法(SPA)的RS码软判决译码的级联码方案。该方案仅需在现有方案的基础上作少量调整即可获得可观的编码增益。和其它流行的软判决译码算法的比较表明,此方案提出的RS码软判决译码算法在DMB-T系统的应用中具有一定的优势。     

基于FPGA的级联编码系统的设计与实现

基于IESS-308标准设计了里德-所罗门码和卷积码的级联编码方案,解决了级联编码系统设计中的关键问题,提出了系统的同步策略,在现场可编程门阵列上实现了整个系统,并在硬件平台上对级联编码系统进行了性能测试。测试结果表明,实测值与理论值一致,从而验证了方案的正确性。该方案具有较强的通用性,经适当修改,可满足其他传输标准的要求。     

Design of Coding and Modulation for Power-Efficient Use of a Band-Limited Optical Channel

We show thatQ-ary pulse-position modulation with raised cosine pulses minimizes the average power (photons/s) required to communicate at a specified throughput rate (nats/s) over a band-limited, noisy optical channel. The best choice ofQis identified, as are other encoder parameters.     

New Table-Switching and Data-Multiplexing Schemes of Rate-Compatible Punctured Convolutional Codes for Unequal Error Protection

In this letter, rate-compatible punctured convolutional (RCPC) codes are further investigated for the application to unequal error protection (UEP). Besides the rate-compatible restriction, we show that puncturing tables should be switched in a special way called soft-switching to guarantee the designed UEP performance. A new data-multiplexing scheme is also proposed for RCPC codes which can achieve similar UEP performance as the conventional scheme but requires no extra zero-padding for frame termination to improve the system throughput.     

Performance of Convolutional Codes With Finite-Depth Interleaving and Noisy Channel Estimates

In this paper, we derive the Chernoff bound of the pairwise error probability (PEP) and the exact PEP of convolutional codes in a time-varying Rician fading channel. With the assumptions that the channel estimator is a finite impulse response filter and the interleaving depth is finite, we are able to investigate the estimation-diversity tradeoff resulting from the effects of the Doppler spread on the system performance via the channel-estimation accuracy and the channel diversity. In addition, we verify that, in the special case when the pilot signal-to-noise ratio is infinitely large and the channel estimator is well-designed, our analysis leads to the same result as the existing perfect channel-state information analysis. Finally, the analytical results are compared with results from Monte Carlo simulation, and the comparison shows that the analytical results match well with the simulation results.     

Rice衰落下RS码级联空时分组码系统的性能分析

从理论上给出一种Rice衰落条件下Reed-Solomon码级联空时分组码系统的差错性能分析方法,并推导给出级联码误比特率上界的数学表达式。理论分析和仿真结果表明,随着信噪比的增加,级联码系统的性能曲线迅速变好,获得了很高的编码增益。在误比特率为10-4时,与Reed-Solomon码的级联可以使衰落条件下空时分组码的性能提高大约5 dB。