Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail.     

Implementation of surface roughness scattering in Monte Carlo modeling of thin SOI MOSFETs using the effective potential

In Monte Carlo simulations of carriers in confined layers, quantum mechanical effects render ineffective the reflection boundary condition method of including surface roughness scattering. Therefore, to include the effects of both the quantum confinement and surface roughness in thin silicon on insulator (SOI) MOSFETs, the surface roughness must be handled differently. In this paper, we include the surface roughness as an additional scattering mechanism in a three-dimensional Poisson-ensemble Monte Carlo simulation that includes the quantum mechanical effects with the effective potential. We find that this method yields appropriate results for both the quantum confinement and surface roughness, provided adequate steps are taken when implementing the surface roughness scattering rate.     

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Conventional Technological Boosters for Injection Velocity in Ultrathin-Body MOSFETs

To meet ITRS requirements, highly scaled MOSFETs will have to operate close to the quasi-ballistic regime and to exhibit enhanced injection velocity. Good performances may be achieved thanks to high transport materials such as germanium or III-V semiconductors. However their integration is still very challenging. Following a different approach, this paper proposes to examine how to improve the injection in conventional (100) silicon ultrathin-body (UTB) MOSFETs. A systematic investigation of the impact of the different usual technological parameters highlights that SG and DG exhibit comparable performances and that no improvement in the injection velocity is expected with the silicon thickness thinning down to 4 nm. Moreover the degradation of the injection velocity with the integration of high- dielectrics is shown. Finally, a significant improvement of the injection velocity due to a higher confinement in asymmetrical double gate MOSFET has been found. Similarly, it is shown that, single gate UTB MOSFETs with thin buried oxide (BOX) exhibit an enhanced injection velocity. In conclusion, only the reduction of the BOX thickness and the integration of strained channel have been found to be realistic and significant boosters of the injection velocity in silicon (100) MOSFETs. Prediction of the evolution of the injection velocity along the roadmap, using a pragmatic strategy of scaling, confirms that these two parameters will play a significant role in improving highly scaled (100) silicon devices performances.     

Threshold voltage calculation in ultrathin-film SOI MOSFETs using the effective potential

The success of the effective potential method of including quantum confinement effects in simulations of MOSFETs is based on the ability to calculate ahead of time the extent of the Gaussian wave packet used to describe the electron. In the calculation of the Gaussian, the inversion layer is assumed to form in a triangular potential well, from which a suitable standard deviation can be obtained. The situation in an ultrathin silicon-on-insulator (SOI) MOSFET is slightly different, in that the potential well has a triangular bottom, but there is a significant contribution to the confinement from the rectangular barriers formed by the gate oxide and the buried oxide. For this more complex potential well, it is of interest to determine the range of applicability of the effective potential model with a constant standard deviation. In this paper, we include this effective potential model in Monte Carlo calculations of the threshold voltage of ultrathin SOI MOSFETs. We find that the effective potential recovers the expected trend in threshold voltage shift with decreasing silicon thickness, down to a thickness of approximately 3 nm.     

Monte Carlo simulation of symmetric and asymmetric double-gate MOSFETs using Bohm-based quantum correction

In light of increasing interest in the development of double gate (DG) CMOS technology that extends the device scaling limit, the relative merit of symmetric versus asymmetry DG-MOSFETs is studied using the quantum corrected Monte Carlo (MC) method. A recently developed Bohm-based quantum correction model is applied to the MC simulation of DG-MOSFETs. The drain current is first studied as the thickness of the silicon layer is scaled. Then results of the charge density and potential for asymmetric and symmetric devices under the same bias conditions are compared. Also analyzed is how the drain induced barrier lowering is affected by the channel length.     

Impact of single charge trapping in nano-MOSFETs-electrostatics versus transport effects

In this paper, using Monte Carlo (MC) simulations featuring ab initio Coulomb scattering, we study the impact of Coulomb scattering from a single trapped electron on the magnitude of the corresponding drain-current reduction in a series of well scaled n-channel nano-MOSFETs. Through a careful comparison with drift-diffusion (DD) simulations that only capture the electrostatic effects associated with the trapped charge, we were able to demonstrate the specific contribution of the scattering. The simulations are performed at low drain bias for MOSFETs with channel lengths of 30, 20, and 10 nm, respectively. Compared to the DD results, the MC simulations show significant additional reduction in drain current associated with the scattering from the trapped electron. The scattering related percentage reduction in the current increases with the increase of the gate voltage toward strong inversion conditions. The velocity distributions in the presence of the trapped charge at various gate conditions are carefully analyzed in order to explain the magnitude of the observed effect.     

Breakdown of universal mobility curves in sub-100-nm MOSFETs

We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model. Owing to the high efficiency of the transport kernel, effective mobility in 3-D MOSFETs with realistic Si-SiO/sub 2/ interfaces reconstructed from a Gaussian or exponential correlation function can be simulated in a statistical manner. We first demonstrate a practical calibration procedure for the interface mobility and affirm the universal behavior in the long channel limit. Next, effective mobility in ensembles of MOSFETs with a gate length down to 10 nm is investigated. It is found that the random-discrete nature of the Si-SiO/sub 2/ interface leads to a distribution of carrier mobility below the interface, which can deviate considerably from universal mobility curves when L/sub gate/<6/spl Lambda/, where /spl Lambda/ is the correlation length for the SiO/sub 2/ interface.     

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.     

Coupled Mechanical and 3-D Monte Carlo Simulation of Silicon Nanowire MOSFETs

In this paper we report on a general methodology to investigate nanowire MOSFETs based on the coupling of mechanical simulation with 3-D real-space Monte Carlo simulation. The Monte Carlo transport model accounts for both strain silicon and quantum mechanical effects. Mechanical strain effects are accounted for through an appropriate change of the anisotropic band structure computed with the empirical pseudopotential method. Quantum effects are instead included by means of a quantum mechanical correction of the potential coming from the self-consistent solution of the Schrodinger equation. This methodology has been then applied to the simulation of a test case silicon nanowire n-MOSFET. Impact of mechanical strain and quantum effects on the drive current is investigated. It is shown that only the inclusion of strain and quantum mechanical effects allows a good agreement with experimental data, demonstrating the validity of the proposed methodology for ultimate devices.     

Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs

Threshold voltage variation due to quantum confinement effect in ultra-thin body silicon-on-insulator (SOI) MOSFETs is examined. It is experimentally demonstrated that threshold voltage variation drastically increases when SOI layer is thinned down to 3 nm. A percolation model is used to estimate the contribution of surface roughness to V/sub th/ variation. The method to suppress the threshold voltage variation is also proposed, and around 15% reduction in threshold voltage variation is experimentally demonstrated by applying substrate bias. The reason of the suppression can be explained by quantum confinement effect induced by substrate bias.     

Experimental Comparison Between Sub-0.1-μm Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility

This paper presents an experimental comparison between single-gate (SG) and double-gate (DG) transistors performance. Using a novel process flow, we managed to cointegrate these two devices on the same wafer with a TiN metal gate. Short-channel effect control, static performance, and mobility are quantified for each architecture. An in-depth mobility study is performed for a wide range of temperatures (10 K-300 K) and gate lengths (10-20 nm) while channel thickness is fixed at 6 nm. This study experimentally highlights the advantages of DG devices over SG transistors. Good mobility values are obtained for both architectures and we show the advantages of ultrathin body devices over bulk transistors. Finally, we demonstrate that Coulomb scattering is the primary cause of the mobility degradation in short-channel devices     

Assessment of high-frequency performance limits of graphene field-effect transistors

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20 nm have been examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is significant for sub-100 nm graphene FETs, it is possible to achieve a good transconductance and ballistic on-off ratio larger than 3 even at a channel length of 20 nm. At a channel length of 20 nm, the intrinsic cut-off frequency remains at a few THz for various gate insulator thickness values, but a thin gate insulator is necessary for a good transconductance and smaller degradation of cut-off frequency in the presence of parasitic capacitance. The intrinsic cut-off frequency is close to the LC characteristic frequency set by graphene kinetic inductance (L) and quantum capacitance (C), which is about 100 GHz·μm divided by the gate length.      

A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage$( V_ th)$, and drain-induced barrier-height lowering are numerically calculated for the device with different channel length ($L$) and the thickness of silicon film$( T_ si)$. Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs,$ T_ si$should be simultaneously scaled down with respect to$L$. From a practical fabrication point-of-view, a DG MOSFET with ultrathin$ T_ si$will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that$ L/ T_ si geq 1$may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.     

Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs

The body effect in ultrathin body (silicon-on-insulator) SOI MOSFETs has been investigated by experiments and modeling. It is demonstrated for the first time that the adjustable threshold voltage range by substrate bias is enhanced due to the quantum confinement effect in ultrathin body SOI. The enhancement ratio of the adjustable threshold voltage range in a 4.3-nm-thick SOI MOSFET compared to 11.7-nm-thick one is around 10%. This indicates that ultrathin body MOSFETs are useful not only for suppressing the short channel effects, but also for suppressing the off-leak current in the variable threshold CMOS scheme.     

The impact of structural parameters on the electrical characteristics of silicon nano wire transistor based on non equilibrium Green's function

In this paper we have used a fully ballistic quantum mechanical transport approach to analyse electrical characteristics of rectangular silicon nanowire field effect transistor in 7 nm gate length. We have investigated the impact of structural parameters of Gate all around Silicon nano wire transistor (GAA-SNWT) on its electrical characteristics in subthreshold regime. In particular we have shown the effect of increasing the Source/Drain and channel length (L(S), L(D) and L(Ch)) on short channel effects as well as change in body thickness and independent back gate voltage. We also investigate the effect of increasing the gate underlap on the electrical characteristics and on the switching speed of device. We show that if the Lun is increased the gate capacitance and DIBL will reduce while the I(ON)/I(OFF) ratio is increased.     

Ultrashort channel silicon nanowire transistors with nickel silicide source/drain contacts

We demonstrate the shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) by a controlled reaction with Ni leads on an in situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 °C. NiSi(2) is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of 17 nm to 3.6 μm. Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs, and that limits transport parameter extraction from SB-FETs using conventional field-effect transconductance measurements.     

Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

The electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs (FXMOSFETs) fabricated by a wet process have experimentally and systematically been investigated. The almost ideal S-slope of 64 mV/decade was obtained for the fabricated 20 nm Si-Fin and 125 nm gate-length FXMOSFET. This excellent subthreshold characteristic shows that the quality of the rectangular Si-Fin channel with (111)-oriented sidewall is good enough to realize high-performance FXMOSFETs. The current and transconductance multiplication accurately proportional to a number of 30 nm Si-Fin channels was confirmed in the fabricated multi-fin FXMOSFETs. The systematic investigation of the electrical characteristics of the fabricated FXMOSFETs in the 20-110-nm Si-Fin and 2.3-5.2-nm gate oxide regimes reveals that short-channel effects can be effectively suppressed by reducing the Si-Fin thickness to 20 nm or less. The developed processes are quite attractive for fabrication of ultranarrow Si-Fin channel double-gate MOSFETs.     

Design of molecular devices based on metalloproteins: a new approach

In this study, cytochrome c and azurin proteins were immobilized onto a porous silicon (PS) surface using the self-assembly technique. The heterostructures were maintained at ambient conditions for several days. Experimental results showed long term stability of proteins in solid state working as electron-transfer devices. Atomic force microscopy showed similar roughness of the surface for both protein heterostructures (14.5 and 11.3 nm, respectively) and globular morphology. Analysis of samples, using scanning electron microscopy, revealed a porous surface of 20–24 nm, whereas cross-section indicated a thickness between 3.6 and 3.8 μm. The fluorescence peak at room temperature, corresponding to blue emission, was observed at 362–550 nm. This is due to the quantum confinement effect through the silicon. Raman measurement showed one Raman’s peak, confirming that the prepared sample retained the crystallinity of bulk silicon; immobilization of proteins produced loss of crystallinity. Reflection spectra revealed the PS, changes in the refractive index profile at the interface of the PS, and the modified surface.