nMOS四值触发器的设计及其应用

本文应用限幅电压开关理论设计了两种主从型ｎＭＯＳ四值触发器。这些触发器具有双端预置能力和双轨互补输出。通过采用ＪＫＬＭ型触发器对十六进制加法计数器和十进制加法计数器的设计实例证明了这些触发器能有效地用于四值时序电路的设计。     

CMOS集成电路应用讲座——第五讲 计数器及应用

CMOS计数器由触发器和门电路组成,包括同步型和非同步型两大类,计数方式有加法计数器,减法计数器,可预置数可逆计数器,可预置数1/N计数器,任意进制计数器,环形计数器等.非同步型计数器是一种串联工作的基本计数器,它的特点是结构简单,计数速度较低,因它不是受同一时钟(CL)控制下工作,所以称它为非同步型计数器.同步型计数器是一种并联工作的计数器,消除了非同步计数器累积的触发延迟,在同步型计数器中,所有触发器是在同一时钟(CL)作用下工作,所以称为同步型的,同步型计数器比非同步     

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。     

产生宽度可变的脉冲群

采用AD9501数字式延时发生器(DDG)可产生宽度可依次增加或减少的脉冲群。本电路用两只74LS193计数器接成加法计数器,由开关PS1复位,初始值OOH由开关PS2锁存入DDG。 输入时钟脉冲的上升沿对触发器,加法计数器和DDG进行置位和触发。DDG将脉冲进行延时,延时间隔与预置脉冲数有关,预置值为OOH时,延时最小,为DDG的最小时延tpd。下一脉冲送入时,加法器输出O1H,时延在tpd基础上     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

奇产生器预置型格雷码计数器的GAL实现

格雷编码的计算机程序存贮器地址总线没能推广的主要问题是格雷码计数器不便于置数.将奇产生电路用于格雷码计数器中,设计了附加位预置型和直接预置型两种可置数格雷码加法计数器.并用GAL16V8对后者进行了加电验证,证实了设计的有效性.     

基于电路三要素理论的2-5混值/十值计数器研究

通过对2-5混值编码原理、电路三要素理论和N +1值代数理论的分析,定量研究了2-5混值门电路、触发器和带进位/借位的加减法计数器,最后设计了2-5混值/十值译码电路,使计数器输出为十值信号。与以往十值电路的设计方法相比较,此设计方案具有编码效率高、供电电压低等特点。计算机模拟验证了上述理论和依此理论设计的电路的正确性。     

基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

任意进制计数电路简易设计

由计数(分频)电路和移存器电路按一定规律排列,可以组成任意进制计数电路.本文首先给出设计举例,然后讨论设计方法.最简电路积木组成任意进制计数器众所周知:移存器可以组成任意进制计数器,时间关系简单,但是需要触发器数目太多;计数译码型电     

基于电路三要素理论的五值计数器研究

本文提出六值代数,建立五值电路三要素理论(信号、网络和负载理论),作为定量研究五值电路的数学工具。在此基础上,首先用δ展开法由五值电路功能直接推出具有复位功能的五值反相器和动态D触发器的元件级结构。然后,对五值计数器进行研究,将其划分为五种类型,并设计出电路结构简单的具有复位功能的五值移位计数器。计算机模拟验证了上述理论和电路的正确性。     

DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS

By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter. Supported by Youth Science & Technology Foundation of Ningbo Science & Technology Commission and by Natural Science Foundation of Zhejiang Province, China     

基于集成计数器的N进制计数器设计与仿真

计数器是一种重要的时序逻辑电路,广泛应用于各类数字系统中。介绍以集成计数器74LS161和74LS160为基础,用归零法设计N进制计数器的原理与步骤。用此方法设计了3种36进制计数器,并用Multisim10软件进行仿真。计算机仿真结果表明设计的计数器实现了36进制计数的功能。基于集成计数器的N进制计数器设计方法简单、可行,运用Multisim 10进行电子电路设计和仿真具有省时、低成本、高效率的优越性。     

TWO-INPUT PRESETTING TECHNIQUE AND DESIGN OF CMOS FLIP-FLOPS WITH A HIGH RADIX

By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information.     

双端置数技术与高值CMOS触发器设计

在分析以往高值触发器困难的基础上本文提出了双端予置的逻辑设计方案。应用传输函数理论对四值CMOS触发器进行了电路设计。结果表明,与存贮相同信息量的二个二值触发器相比,它有较简单的结构与较快的工作速度。     

Modulo-N counter technique for the u.h.f. band

A technique is described for implementing modulo-N counters with u.h.f. performance using commercially available e.c.l. components and a high-speed digital multiplexer. A modulo-5 counter is designed according to this technique and performance at 1.6 GHz is demonstrated.     

Conditional-capture flip-flop for statistical power reduction

This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-μm CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop     

反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

Low-power sequential circuit design using T flip-flops

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.     

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.     

Design of a divide-by-N asynchronous odd-number counter with 50/50 duty cycle

Methods of designing an asynchronous divide-by-N odd-number counter with 50/50 duty-cycle output are presented. The counter can be implemented by an EXCLUSIVE OR gate associated with a divide-by-(N + 1)/2 counter and a flip-flop, or by the combination of EXCLUSIVE OR gates and flip-flops.