Performance of a nonblocking space-division packet switch withcorrelated input traffic

This work studies the performance of a nonblocking space-division packet switch in a correlated input traffic environment. In constructing the input traffic model, the author considers that each input is a time division multiaccess (TDM) link connecting to multiple sources. Every source on a link supports one call at a time. Each call experiences the alternation of ON and OFF periods, and generates packets periodically while in ON period. The stochastic property of each call does not have to be identical. Packets from each individual call are destined to the same output. The output address of each call is assumed to be uniformly assigned at random. The author derives both upper and lower bounds of the maximum throughput at system saturation. His study indicates that, if the source access rate is substantially lower than the link transmission rate, the effect of input traffic correlation on the output contentions can generally be ignored. Also, the analysis of each input queue becomes separable from the rest of the switch. The same study is carried out with nonuniform call address assignment     

Photonic 2*2 packet switch with input buffers

A self-routing 2*2 photonic packet switch with two fibre-loop input buffers that provide output contention resolution is demonstrated. The switch uses high-speed electronic control that prioritises all switching and buffer operations and guarantees packet integrity while maximising throughput.<>     

Performance of a nonblocking space-division packet switch in a timevariant nonuniform traffic environment

The authors study the performance of a nonblocking space-division packet switch, given that the traffic intensities at the switch not only are nonuniform but also change as a function of time. A finite-state Markov chain is used as an underlying process to govern the time variation of traffic for the entire switch. The packet arrivals at each input form an independent Bernoulli process modulated by the underlying Markov chain. The output address of each packet is independently and randomly assigned with probability distributions, which are also modulated by the Markov chain. Provided that the traffic on each output is not dominated by individual inputs the service time of each output queue for sufficiently large switches can be characterized by an independent Markov modulated phase-type process. A matrix geometric solution for the resultant quasi-birth-death type queuing process is presented. The maximum throughput is obtained at the system saturation. The performance of the switch is numerically examined under various traffic conditions. A contention priority scheme to improve the switch performance is proposed     

Tandem-crosspoint ATM switch with input and output buffers

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch, The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

Throughput analysis, optimal buffer allocation, and trafficimbalance study of a generic nonblocking packet switch

A general model is presented to study the performance of a family of space-domain packet switches, implementing both input and output queuing and varying degrees of speedup. Based on this model, the impact of the speedup factor on the switch performance is analyzed. In particular, the maximum switch throughput, and the average system delay for any given degree of speedup are obtained. The results demonstrate that the switch can achieve 99% throughput with a modest speedup factor of four. Packet blocking probability for systems with finite buffers can also be derived from this model, and the impact of buffer allocation on blocking probability is investigated. Given a fixed buffer budget, this analysis obtains an optimal placement of buffers among input and output ports to minimize the blocking probability. The model is also extended to cover a nonhomogeneous system, where traffic intensity at each input varies and destination distribution is not uniform. Using this model, the effect of traffic imbalance on the maximum switch throughput is studied. It is seen that input imbalance has a more adverse effect on throughput than output imbalance     

Design implementation of ATM switch with input priority anddistributed output buffers

A switch architecture for ATM is described which uses a simple priority module to resolve input contention and a distributed design to permit transfer of input cells to the first free output buffer. The switch has been synthesised using VHDL software and a target generic library and can operate at speeds >400 Mbit/s     

Performance of a packet switch with crossbar architecture

A packet having a crossbar architecture with M inputs and N outputs is considered. Following earlier work, the theoretical capacity of such a switch is found in terms of the throughput of a closed queueing network. A state-dependent server model that approximates the rate at which the switch is transferring packets as a function of the work backlog (the number of packets queued at the switch inputs) is then developed. In this way, the model reflects the fact that such a switch tends to function more efficiently as the work backlog increases. This model yields an accurate method for approximating the entire distribution of the work backlog, as well as mean queue lengths and waiting times     

Performance analysis of the multiple input-queued packet switch with the restricted rule

The multiple input-queued (MIQ) switch is the switch which manages multiple (m) queues in each input port, each of which is dedicated to a group of output ports. Since each input port can switch up to m cells in a time slot, one from each queue, it hardly suffers from the head-of-line (HOL) blocking which is known to be the decisive factor limiting the throughput of the single input-queued (SIQ) switch. As a result, the MIQ switch guarantees enhanced performance characteristics as the number of queues m in an input increases. However, the service of multiple cells from an input could cause internal speedup or expansion of the switch fabric, diluting the merit of high-speed operation in the conventional SIQ scheme. The restricted rule is contrived to circumvent this side effect by regulating the number of cells switched from an input port. We analyze the performance of the MIQ switch employing the restricted rule. For the switch using the restricted rule, the closed formulas for the throughput bound, the mean cell delay and average queue length, and the cell loss bound of the switch are derived as functions of m, by generalizing the analysis for the SIQ switch by J.Y. Hui and E. Arthurs (see IEEE J. Select. Areas Commun., vol.SAC-5, p.1262-73, 1987).     

Maximum throughput of an input queueing packet switch with twopriority classes

The maximum throughput of an N×N nonblocking packet switch with input queues and two priority classes is analyzed. Packets are of fixed length and the switch operation is slotted. Packets of both priority classes are queued when waiting for service. High-priority packets preempt low-priority ones and move ahead of all low-priority packets waiting in the queue. A new method of analysis is employed. The calculated results of the maximum throughput obtained are close to the simulation results     

Performance of a broadcast packet switch

The results of a simulation study undertaken to evaluate a high-performance packet-switching fabric supporting point-to-point and multipoint communications are presented. This switching fabric contains several components, each based on conventional binary routing networks. The most novel element is the copy network, which performs the packet replication needed for multipoint connections. Results characterizing the performance of the copy network are presented. Several architectural alternatives for conventional binary routing networks are also evaluated. For example, the performance gains obtainable by using cut-through switching in the context of binary routing networks with small buffers are quantified. One surprising result is that networks constructed from nodes with more then two input and output ports can perform less well than those constructed from binary nodes. This result is quantified and explained     

Performance trade-offs in input/output buffer design for a non-blocking space-division packet switch

Performance trade-offs in buffer architecture design for a space-division packet switching system is studied. As described in Figure 1, the system is constructed by a non-blocking switch fabric and input/output buffers. The capacity of the non-blocking switch fabric is defined by the maximum number of packets, denoted by m, which can be simultaneously routed from multiple inputs to each output. The buffer size at each input is considered to be finite, equal to K. The emphasis here is placed on the input packet loss probability for systems constructed by different ms and Ks. From the performance point of view, we conclude:

• (a) choosing m = 3 or 4 is sufficient to exploit the maximum utilization of a non-blocking switch fabric
• (b) introducing input buffers of moderate size K significantly reduces the packet loss probability.

     

The performance analysis and implementation of an input accessscheme in a high-speed packet switch

The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n ² input queues in an (n×n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds     

A cellular neural network for packet selection in a fast packetswitching fabric with input buffers

We propose an implementation in terms of a cellular neural network (CNN) of the packet selection discipline in an input queueing fast packet switching (FPS) fabric. A neural network is designed which is devoid of spurious (suboptimal) responses and is guaranteed to take optimal decisions for switching packets. Such a neural network permits to lower the buffer memory requirements and to achieve throughput-mean switching delay performance close to the optimum (output) queueing alternative     

Performance study on a WDM packet switch with limited-rangewavelength converters

We consider a slotted WDM packet switch with limited-range wavelength converters. The performance of this switch is studied using simulations with various types of data traffic. Results show that the slotted WDM packet switch with a small range of wavelength conversion capability can achieve a performance close to that of a switch with the full range of wavelength conversion capability     

具有反馈式光缓存的OPS节点结构性能研究

对反馈式光分组交换节点的性能进行深入分析,并针对现有反馈式光分组交换节点结构的不足,提出一种改进的反馈式光分组交换节点结构,即SMOP-TWC交换结构.最后,本文使用仿真实验的方法对SMOP-TWC交换结构的性能进行深入研究.     

Analysis of nonblocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation     

Using a packet switch for circuit-switched traffic: a queueingsystem with periodic input traffic

Consideration is given to the effects of time-multiplexed stream traffic on the performance of a store-and-forward packet switch. Substantially reducing the amount of buffering in the switch results in only a small probability that an existing circuit will be disrupted during the length of its connection. For example, with a circuit-switched frame of length 1000 and 100% loading, reducing the buffer size from 999 packets to 83 results in only a 10^-6 circuit-disruption probability     

Stochastic analysis of gradient adaptive identification ofnonlinear systems with memory for Gaussian data and noisy input andoutput measurements

This paper investigates the statistical behavior of two gradient search adaptive algorithms for identifying an unknown nonlinear system comprised of a discrete-time linear system H followed by a zero-memory nonlinearity g(·). The input and output of the unknown system are corrupted by additive independent noises. Gaussian models are used for all inputs. Two competing adaptation schemes are analyzed. The first is a sequential adaptation scheme where the LMS algorithm is first used to estimate the linear portion of the unknown system. The LMS algorithm is able to identify the linear portion of the unknown system to within a scale factor. The weights are then frozen at the end of the first adaptation phase. Recursions are derived for the mean and fluctuation behavior of the LMS algorithm, which are in excellent agreement with Monte Carlo simulations. When the nonlinearity is modeled by a scaled error function, the second part of the sequential gradient identification scheme is shown to correctly learn the scale factor and the error function scale factor. Mean recursions for the scale factors show good agreement with Monte Carlo simulations. For slow learning, the stationary points of the gradient algorithm closely agree with the stationary points of the theoretical recursions. The second adaptive scheme simultaneously learns both the linear and nonlinear portions of the unknown channel. The mean recursions for the linear and nonlinear portions show good agreement with Monte Carlo simulations for slow learning. The stationary points of the gradient algorithm also agree with the stationary points of the theoretical recursions