采用CORDIC算法的直接数字频率合成器的设计

为了实现CORDIC（Coordinate Rotation Digital Computer）算法在DDS（Direct Digital Frequency Synthesis）中的应用,文章介绍了CORDIC算法的一般法则和DDS的基本结构,提出了一种流水线型的CORDIC算法,并应用于FPGA（Field Programmable Gate Array）设计中,最后给出了基于ModelSim的仿真结果。     

A Modified CORDIC FPGA Implementation for Wave Generation

This paper presents a modified coordinate rotation digital computer (CORDIC) algorithm implemented in parallel architecture to generate sine and cosine waveform. Since CORDIC is a combination of only additions and shifts, it can be efficiently implemented in hardware. The proposed algorithm further approximates the way of computing rotation angle based on Taylor series in order to reduce the usage of Read-Only-Memory (ROM) table. Thus area and power is reduced due to partial usage of ROM storage. The precision remains the same as the original algorithm. The modified 32-bits pipeline CORDIC are implemented in Spartan XC3S500E device using Xilinx ISE 12.3 design suite. The result is compared with original CORDIC and Xilinx coregen in device utilization. It is shown that the logic usage is 31 FFs and 285 FFs less than the original design and Xilinx core, respectively. When compared with the original design, the signal power and total power reduction at 40 MHz clocks are 7.69 % and 1.35 %, respectively. The bit error remains at 10^?8 dB level. The SNR of modified CORDIC is about 2 dB lower, which is acceptable in wave generation.     

直接数字频率合成器的设计及FPGA实现

直接数字频率合成器(DDS)通常使用查表的方法实现相位和幅值的转换，文章介绍了一种基于CORDIC算法的DDS。CORDIC算法在三角函数合成上有着广泛的用途，作者从DDS的一般结构和CORDIC算法的基本原理出发．深入探讨了基于CORDIC算法的DDS各部件的结构和FPGA实现。     

High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method

This paper presents architectural and algorithmic approaches for achieving high-speed CORDIC processing in both of the two operating modes: vectoring and rotation. For vectoring mode CORDIC processing, a modified architecture is proposed, which aims at reduction of computation time by overlapping the stages for redundant addition and selection of rotation direction. In addition, a novel rotation direction prediction scheme for rotation mode CORDIC is presented. The method is based on approximation of the binary angle input to a number with the arctangent weights (tan^–1 2^–i). The implementation is designed to keep the fast timing characteristics of redundant arithmetic in the x/y path of the CORDIC processing. The characteristics are analyzed with respect to latency time and area, and compared with those obtained by conventional CORDIC implementations. The results show that the proposed techniques reduce not only the block latency but also the overall computation time. Thus, they achieve higher throughput in pipelining.     

Digit-pipelined direct digital frequency synthesis based on differential CORDIC

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed.     

基于CORDIC算法的流水线型DDS设计

信号源是电子系统中重要的组成部分。随着电子技术的不断发展,对信号源的要求越来越高,传统的模拟信号源已经远远不能满足要求,而直接数字合成技术的出现,给现代电子技术带来了新的生机。文章在分析了DDS原理、CORDIC算法原理的基础上,提出了一种基于CORDIC算法的全流水线型DDS结构。使用verilogHDL编写了RTL级代码,并进行了综合、布局布线、后仿真验证等。工作频率为176.65MHz,输入频率控制字为48位,输出幅度为16位,频率分辨率为6.27×10-7Hz。     

基于CORDIC算法的流水型DDS设计与研究

在分析CORDIC算法原理基础上,提出了一种基于CORDIC算法的流水型DDS结构,用以取代传统的ROM查找表法。同时对输入角度进行预处理,对迭代结果进行后处理,实现了整个周期的三角函数计算。设计采用verilog语言描述,在QuartusⅡ9．0下编译综合,以及Modelsim-altera6．4进行了仿真。结果表明,该算法比传统算法具有计算角度范围大、高速度和低资源的优势。     

Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8?×?N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.     

基于CORDIC算法的优化的直接数字频率合成器

介绍了一种用CORDIC(坐标旋转数字计算机)算法模块替代DDS(直接数字频率合成器)中ROM表的方法.应用这种方法可以极大地减小存储量,取消存储量对提高数据精度的限制,提高DDS的性能.对这种方法进行了理论分析,并用一个设计例子得出了仿真结果,证实这种方法的可行性,最后简要介绍了这种结构的FPGA(现场可编程门阵列)设计方法.     

一种改进超四算法的DDS设计

为了提升直接数字频率合成器(Direct Digital Synthesizer,DDS)的性能,针对DDS的相幅转换器进行了改进。基于坐标旋转数字计算算法(Coordinate Rotation Digital Computer Algorithm,CORDIC),利用三角函数角度近似的性质和相位寻址位与旋转角度的转换关系对超四算法改进,得到了仅需一次单向旋转的改进算法,并给出了该算法实现的电路结构。通过Matlab仿真分析,该电路无杂散动态范围值可以达到-119. 1 dBc,输出误差小于1. 05×10^-5。基于Xilinx的FPGA平台进行仿真实验,结果表明该电路结构的输出延时不超过21 ns,相比其他类型的CORDIC算法提升了近48!的速度,同时面积资源也明显减少。该设计可以为雷达、通信等系统优化提供新的思路。     

A unified reconfigurable CORDIC processor for floating-point arithmetic

ABSTRACT

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.     

基于CORDIC算法的DDS实现

直接数字频率合成(DDS)技术在软件无线电方面有着广泛的应用,而坐标旋转数字计算方法(Coordinate Rotation Digital Computer,CORDIC)通过移位和加减运算代替乘法运算是构造DDS的一种理想的手段。介绍了CORDIC算法的基本原理,采用流水线方法对CORDIC算法进行了设计实现,用以取代传统的ROM查找表法。实验验证,基于CORDIC算法的DDS满足高速、高精度、高分辨率和实时运算的要求。     

一种高性能数字下变频硬件计算结构

数字下变频是软件无线电的核心技术,随着通信技术的发展,如今对其处理速度要求越来越高。现提出了一种高性能的数字下变频硬件计算结构,使用CORDIC,流水线划分,重定时等技术来优化数字下变频各个模块的硬件结构。通过和传统设计方案的实验比较,证明了本方案能在将FPGA总体资源使用等效门数减少29．54％的情况下,将最高数据吞吐率提升6．74倍。     

基于CPLD／FPGA的AES算法混合流水实现

在加解密算法的硬件实现中,使用流水线结构可以显著地提高加密解密速度,但是由于这类结构并不适合于大多数的反馈模式,因而此类结构在当前密码学中的应用较少。为此,该文采用一种补偿手段,基于交叉CBC(Interleaved Cipher Block Chaining)模式,以混合流水结构成功地实现了AES(Advanced EncryptionStandard)的算法。该方案允许并行处理4个数据块(称为一次加密或解密),同时两次加密或解密之间还可实现部分并行。该方案在EP20k300EBC652-1(Ateral公司产品)上已得到成功验证。     

Pipelining flat CORDIC based trigonometric function generators

Despite further refinements of the CORDIC algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains to be the major bottleneck for further optimization. A technique known as flat CORDIC, in which the conventional X and Y recurrences are successively substituted to express the final vectors in terms of the initial vectors, can be used to eliminate the iterative process. In this paper, the techniques devised for the VLSI efficient implementation of a pipelined 16-bit flat CORDIC based sine–cosine generator are presented. Three possible schemes to pipeline the 16-bit flat CORDIC design have been presented to demonstrate the suitability of the proposed method to realize high throughput implementations. The 16-bit architecture has been synthesized with 0.35 μ CMOS process library using Synopsys. Finally, a detailed comparison with other major contributions show that the flat CORDIC based sine–cosine generators are, on average, 30% faster and occupy some 30% less silicon area.     

用于SAW无线无源传感系统阅读器的DDS设计

直接数字频率合成器(DDS)具有转换时间快,频率精度高,频带宽等特点,作为现代电子设备的重要部分,现已广泛应用于电子领域。该设计将现场可编程门阵列(FPGA)与DDS相结合,采用自顶向下的模块化设计思想、反馈网络的流水线结构及频率自增设计,以达到扫频效果,并基于CORDIC算法实现相-幅转换,以降低硬件资源消耗,最终在Quartus Ⅱ开发环境中进行仿真测试。经CORDIC算法计算后输出的正弦波和余弦波幅值分别为32 768和56 758(16位十进制),输出的正弦和余弦值与预期结果相比,其相对误差仅为6.1×10^-5和9.9×10^-5。仿真结果表明,该设计方案能有效地解决传统声表面波无线无源传感系统中DDS杂散分量大,时延高及功耗高等问题。     

A CORDIC processor for FFT computation and its implementation usinggallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 μm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 μs, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors     

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence

This paper focuses on developing an area efficient hyperbolic Coordinate Rotation Digital Computer (CORDIC) algorithm with performance improvement. The algorithm eliminates the need of scale factor calculation in the Range of Convergence (ROC). At the same time the range of convergence offered is higher than the conventional CORDIC ROC in the hyperbolic rotation mode. Being the only kind of algorithm in hyperbolic rotation with sign sequence μ?=?1 always, one complete operation requires just 5 iterations. Thus the pipelined implementation has 5 stages which provides a 50% increase in throughput in comparison to conventional CORDIC. As far as the area improvement is considered, 16-bit processor can be realized using 56% less number of full adders required by Flat-CORDIC. The x and y datapath are based on series expansion of hyperbolic functions. The complete algorithm design along with pipelined architecture implementation is detailed.     

Design of VLSI Architecture of Autocorrelation-Based Lossless Recompression Engine for Memory-Efficient Video Coding Systems

In this paper, an autocorrelation-based lossless recompression (ABLR) algorithm is proposed. The ABLR can save the memory bandwidth of video coding systems and preserves the visual quality. The ABLR consists of two core techniques: (1) a correlation-based prediction technique and (2) a correlation-adaptive Golomb-Rice code. Furthermore, dual-mode memory addressing (DMMA) is also proposed to provide ABLR with memory random access functionality. The word-length utilization rate (WLUR) of DMMA is as high as 92.34 % on average. The experimental results reveal that the ABLR exhibits a lossless compression ratio of 2.05 on average for 1080p test sequences. This indicates that the memory bandwidth can be saved up to 50 %. The VLSI architecture of ABLR is designed with three-stage pipelining and is realized in 0.18 μm 1P6M CMOS technology with a cell-based design flow. The logic gate count is about 28 K and the core area is 0.69×0.68 mm². The encoding capability can reach full HD (1920×1080)@30 fps at a clock rate of 62.5 MHz. The power dissipation is 9.35 mW at a clock rate of 62.5 MHz.     

Novel cell architecture for high performance digit-serial computation

A cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feedforward of the carry digit, which allows a high level of pipelining to increase the throughput rate. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. The effect of the number of pipelining levels on the throughput rate and hardware cost are presented.<>