A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.

     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

Silicon wafers have been anodically bonded to sputtered lithium borosilicate glass layers (Itb 1060) at temperatures as low as 150–180 °C and to sputtered Corning 7740 glass layers at 400 °C. Dependent on the thickness of the glass layer and the sputtering rate, the sputtered glass layers incorporate compressive stresses which cause the wafer to bow. As a result of this bowing, no anodic bond can be established especially along the edges of the silicon wafer. Successful anodic bonding not only requires plane surfaces, but also is determined very much by the alkali concentration in the glass layer. The concentration of alkali ions as measured by EDX and SNMS depends on both the sputtering rate and the oxygen fraction in the argon process gas. In Itb 1060 layers produced at a sputtering rate of 0.2 nm/s, and in Corning 7740 layers produced at sputtering rates of 0.03 and 0.5 nm/s, respectively, the concentration of alkali ions in the glass layers was sufficiently high, at oxygen partial pressures below 10^-4 Pa, to achieve anodic bonding. High-frequency ultrasonic microanalysis allowed the bonding area to be examined non-destructively. Tensile strengths between 4 and 14 MPa were measured in subsequent destructive tensile tests of single-bonded specimens.     

Packaging of a 3-axial piezoresistive force sensor with backside contacts

In this paper design aspects and challenging packaging solution of a monolithic 3D force sensor will be presented. The previously developed design and process flow (Vázsonyi et al. 123–124:620–626, 2005; Molnár et al. 90:40–43, 2012) were improved by an additional hybrid wafer bonding step of simultaneous anodic and metal bonding processes. This electrostatic force assisted metal bonding can ensure both the mechanical and the electrical integrity of the device. The applied novel process sequence can eliminate the need of a possible flip-chip bonding and chemical–mechanical polishing steps. The applied glass substrate improves the thermal isolation and thermo-mechanical stability of the integrated system considering the thermal expansion coefficients of the chosen glass material and the silicon (Si) only slightly differ minimizing the residual thermo-mechanical stress during the operation.     

Fabrication method of spacers with high aspect ratio – Used in a field emission display (FED)

Glass to glass anodic bonding using a metal interlayer was used to develop a fabrication method of spacer for field emission display (FED). In this paper, spacers with width 100 μm and height 1000 μm and a 3.54 inch mono color anode plate patterned with Al/Cr film as an interlayer were bonded by the anodic bonding. To bond the spacers on the anode plate vertically, two types of spacer holders were designed and fabricated with photoetchable glass and n(110) Si wafer. The spacer holder using Si wafer was used to fabricate for evacuated FED panel. Received: 22 November 1999/Accepted: 27 January 2000     

Glass frit bonding: an universal technology for wafer level encapsulation and packaging

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.     

A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Transfer of small structures by bonding

The work presented in this paper deals with the bonding of small structures, down to 1 μm. Its aim is to evaluate the dimensional limits of anodic bonding between silicon and pyrex 7740 glass. Test structures consisting in silicon pillars with controlled radii have been developed. The silicon pillars have been fabricated by deep reactive ion etching to allow a good geometry control of the structures. A collection of matrices of 3×3 identical silicon test structures with dimensions from 200 to 1 μm has been fabricated to determine the smallest area that can bond anodically. The test results have been applied to the transfer of small structures from one wafer to another wafer by bonding, with the final objective of transferring tips for AFM probes. From the test results, a new test for bonding has been defined, based on the pull test of small structures with controlled dimensions. Preliminary simulations by FEM of the pull test of the test structures are in agreement with the experimental results. The test has been used to determine the effect of the voltage and temperature conditions during the anodic bonding on the bond strength.     

Characterization of low-temperature wafer bonding using thin-film parylene

This paper presents detailed experimental data on wafer bonding using a thin Parylene layer, and reports results on: 1) bond strength and its dependence on bonding temperature, bonding force, ambient pressure (vacuum), and time, 2) bond strength variation and stability up to two years post bond, and 3) bond strength variation after exposure to process chemicals. Wafer bonding using thin (<381 nm) Parylene intermediate layers on each wafer in a standard commercial bonder and aligner has been successfully developed. The Parylene bond strength is optimized at 230/spl deg/C, although Parylene bonding is possible at as low as 130/spl deg/C. The optimized bonding conditions are a low-temperature of /spl sim/230/spl deg/C, a vacuum of /spl sim/ 0.153 mbar, and 800 N force on a 100 mm wafer. The resultant Parylene bond strength is 3.60 MPa, and the strength for wafers bonded at or above 210/spl deg/C is maintained within 93% of its original value after two years. The bond strength is also measured after exposure to several process chemicals. The bond strength was reduced most in undiluted AZ400K (base) by 69% after one week, then in BHF (acid), MF319 (base), Acetone (solvent), and IPA (solvent) by 56%, 33%, 20%, and 8%, respectively, although less than one hour exposure to these chemicals did not cause a significant bond strength change (less than 11%). [1487].     

Low cost anodic bonding for MEMS packaging applications

Anodic bonding of Pyrex 7740 glass to bare silicon and oxidized silicon wafer is presented for micro electro mechanical systems (MEMS) device packaging. Experimentally it has been observed that anodic bonding process parameters are varying with different 3D structures. The effects of bonding temperature and voltage are discussed by keeping the temperature constant and varying the voltage. The bonding interface has been studied by scanning electron microscope observations. Effective parameters for MEMS structure such as bonding temperature, voltage has been discussed.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.