Depassivation of latent plasma damage in pMOS devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

Depassivation of latent plasma damage in devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Anomalous gate oxide conduction on isolation edges: analysis and process optimization

In this paper we report a detailed characterization of anomalous gate oxide conduction on isolation edges. Previously, it was shown that gate oxide can feature severe thickness variation [Liu et al., Proceedings of VLSI Symposium, 1999, p. 75; Mat. Res. Soc. Symp. 611 (2000) C4.1.1] near the top corner of the shallow trench isolation. Here, we show that this can significantly impact the tunnel I–V characteristics of gate oxide, with implications for the device performance uniformity and reliability. Comparing experimental data with accurate tunnel current simulation we demonstrate that this anomalous conduction is due to a double effect of oxide thinning and rounding of the poly/oxide interface. Furthermore, we study the impact of many process parameters on this anomalous leakage. We show that, by optimizing several process steps, it is possible to avoid this problem. Possible physical causes of this phenomenon are also addressed.     

A comparative analysis of substrate current generation mechanisms in tunneling MOS capacitors

This paper presents a critical analysis of the origin of majority and minority carrier substrate currents in tunneling MOS capacitors. For this purpose, a novel, physically-based model, which is comprehensive in terms of impact ionization and hot carrier photon emission and re-absorption in the substrate, is presented. The model provides a better quantitative understanding of the relative importance of different physical mechanisms on the origin of substrate currents in tunneling MOS capacitors featuring different oxide thickness. The results indicate that for thick oxides, the majority carrier substrate current is dominated by anode, hole injection, while the minority carrier current is consistent with a photon emission-absorption mechanism, at least in the range of oxide voltage and oxide thickness covered by the considered experiments. These two currents appear to be strictly correlated because of the relatively flat ratio between impact ionization and photon emission scattering rates and because of the weak dependence of hole transmission probability on oxide thickness and gate bias. Simulations also suggest that, for thinner oxides and smaller oxide voltage drop, the photon emission mechanism might become dominant in the generation of substrate holes.     

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented.     

Dependence of plasma-induced oxide charging current on Al antennageometry

The dependence of the plasma-induced oxide charging current on Al electrode geometry has been studied. The stress current is collected only through the electrode surfaces not covered by the photoresist during plasma processes and therefore is proportional to the edge length of the electrode during etching and proportional to the electrode area during photoresist ashing. Knowing the measured oxide charging currents, one should be able to predict the impact of these processes on oxide integrity and interface stability for a given antenna geometry more accurately     

Can macroscopic oxide thickness uniformity improve oxidereliability?

In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for both Weibull parameters, namely, the characteristics times (T₆₃) and Weibull slopes (β) over a wide range of oxide thickness. A detailed full-scale Monte Carlo analysis is used to examine the breakdown characteristics at low-percentile and its sensitivity to variation of thickness dependence of time-to-breakdown and Weibull slopes. We show that for thinner oxides with very shallow Weibull slopes the impact of thickness variation is drastically reduced as compared to thicker oxides for the same parameters     

Design-for-Manufacture for Multigate Oxide CMOS Process

Design-for-manufacture (DFM) for thick gate oxide layout in a dual gate oxide product is investigated. Careless placement and layout for thick gate oxide transistors in the multigate oxide chip can cause significant yield loss. The root cause of the yield loss is that the thick gate oxide can impact the uniformity of the adjacent thin gate oxide thickness. Further experiments' results show that the optimization of thick gate oxide transistor layout for the same product can improve the yield. Besides tweaking the gate oxide etching process to overcome the difficulty of multi oxide product manufacture, the guidelines for a good gate oxide layout practice are provided to facilitate the manufacture.     

Negative charge induced degradation of PMOSFETs with BF/sub 2/-implanted p/sup +/-poly gate

A new degradation phenomenon on thin gate oxide PMOSFETs with BF/sub 2/ implanted p/sup +/-poly gate has been demonstrated and investigated. The cause of this type of degradation is a combination of the boron penetration through the gate oxide and charge trap generation due to the presence of fluorine in the gate oxide and some other processing-induced effects. The negative charge-induced degradation other than enhanced boron diffusion is studied in detail here. The impact of this process-sensitive p/sup +/-poly gate structure on deep submicron CMOS process integration has been discussed.<>     

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures.     

Weibull breakdown characteristics and oxide thickness uniformity

In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for both Weibull parameters, namely, the characteristic times and Weibull slopes over a wide range of oxide thicknesses. We report the abnormal characteristics of the Weibull time-to-breakdown distributions and non-Poisson area scaling behavior observed on ultrathin oxides. Two numerical methods using the parameters obtained from two independent sets of experimental results are developed to quantitatively explain these effects in the context of current modulation due to oxide thickness variation. The relationship between time-to-breakdown and charge-to-breakdown distributions has been clarified and established. It is found that without proper treatment of these effects, the use of Weibull slopes at higher failure percentiles can lead to erroneous and pessimistic reliability projection. Furthermore, me perform a detailed full-scale Monte Carlo analysis to evaluate the impact of thickness variation on low-percentile breakdown distributions and their sensitivity to the thickness dependence of the times-to-breakdown and Weibull slopes.     

Modelling methodology of silicon oxidation from quantum calculations to Monte Carlo level

The atomic scale understanding of silicon oxide growth is investigated to determine interface defects formation (geometry and spatial distribution) during a technology process. In this paper we present a general methodology also applicable to other atomic scale problems. This methodology is based on the use of several theoretical models used in cascade, each model giving parameters for a higher modelling level. To clarify this procedure, we give quantum calculation results and their impact on a Monte Carlo technique to investigate oxide growth dynamics.     

Study of MOS gate dielectric breakdown due to drain avalanche breakdown

This work reports the effects of drain impact ionization injection on the gate dielectric breakdown. Results show that due to the high energy hot carrier injection, the gate oxide can break down twice at a low oxide electric field (<1.2 MV/cm). The first breakdown occurs simultaneously with the drain avalanche breakdown whereas the second breakdown occurs beyond the drain breakdown. It is further identified that the first gate oxide breakdown is governed by the thermionic emission of hot electrons at low oxide fields (<1.0 MV/cm) and by the scattering processes at higher oxide fields. The second breakdown is attributed to the Fowler–Nordheim (F–N) tunneling.     

Measurement of hole leakage and impact ionization currents in bistable metal—tunnel-oxide—semiconductor junctions

The electron tunneling, oxide hole transport, and hot-electron impact ionization currents in bistable metal-tunnel-oxide-semiconductor (MTOS) junctions have been measured using a novel charge-coupled device charge packet insertion transient technique, and by steady-state hole injection. Good agreement was obtained between the two techniques. An electron-to-hole oxide current ratio in the range of 20-40 was observed for a 33-Å tunnel oxide. In addition, the impact ionization hole generation current was found to be 2-5 percent of the electron tunneling current. This excess hole generation appears to be balanced in the stable high current state by back diffusion from a super-inverted semiconductor surface. The impact ionization phenomenon results in a newly discovered voltage controlled n-type negative resistance when the MTOS junction is coupled to an adjacent p-n junction through the use of an intermediate control gate.     

Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs

The impact of the gate oxide and the silicon-on-insulator (SOI) body thickness on the electrical performance of SOI Schottky-barrier (SB) MOSFETs with fully nickel silicided source and drain contacts is experimentally investigated. The subthreshold swing S is extracted from the experimental data and serves as a measure for the carrier injection through the SBs. It is shown that decreasing the gate oxide and body thickness allows to strongly increase the carrier injection and hence, a significantly improved on-state of SB-MOSFETs can be obtained     

异质栅单Halo沟道SOI中隐埋层对器件特性的影响

研究异质栅单Halo沟道SOI MOS器件的隐埋层中二维效应对器件特性,如电势分布、阈值电压等的影响,仿真结果表明,隐埋层中的二维效应会引起更明显的SCE及DIBL效应.在考虑隐埋层二维效应的基础上,提出了一个新的二维阈值电压模型,能较好地吻合二维器件数值模拟软件Medici的仿真结果.     

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.     

Hot hole gate current in surface channel PMOSFETs

This paper reports the observation of a new hot hole component of the gate current of p⁺-poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate, and substrate bias on devices featuring different oxide thickness and drain engineering options. The new hole gate current component is ascribed to injection into the oxide of substrate tertiary holes, generated by an impact ionization feedback mechanism similar to that responsible of CHannel Initiated Secondary ELectron injection (CHISEL) in nMOSFETs