Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits

We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.     

Josephson latching driver with a low bit-error rate

A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.     

Output interface with latching driver for LTS-SFQ circuits

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

Experimental demonstration of single flux quantum logic withresettable latch

We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of “half adder” based on SFQ-RL with the bias margin of ±16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and “circular buffer” with the bias margin of ±20%     

A series of new circuits based on CFTAs

The paper presents a series of basic circuits based on CFTAs (current follower transconductance amplifier), which contain amplifier, lossless integrator, first-order universal current-mode filter, simulation resistor, negative resistance converter, gyrator, capacitor multiplier, and frequency-dependent negative resistance circuit. Having used canonic number of grounded capacitors and resistors, the circuits are easy to be integrated and the parameters of the circuits can be adjusted electronically by tuning bias currents of the CFTAs. It is noted that the results of circuit simulations are in agreement with theory.     

A new driver circuit for chip-to-chip signal transmission in Josephson packaging

A new driver circuit is developed for chip-to-chip logic signal transmission in Josephson computers. Multiple reflection noises between driver and connector impedance discontinuities may cause false logic operations in the driver and receiver circuits. Based on this factor, the driver is designed to match the impedance between the driver and transmission line in order to reduce multiple reflections. Since the noises due to the first reflections remain in this driver system, its use is limited to special cases. When used in these cases, however, the driver provides a shorter transmission path delay than Klein's driver. Experimentation shows that the driver has perfect impedance matching effects within a wide bias current margin (±26 percent).     

超导SFQ电路间脉冲传输的研究

在超导单磁通量子(Single Flux Quantum,SFQ)数字电路版图设计中,电路单元之间的SFQ脉冲传输设计是十分关键的部分之一.讨论传输线作为SFQ数字电路单元之间互联结构的基础上,提出了适用于SFQ数字电路单元之间互联传输线的匹配电路计算公式.仿真结果表明:根据这一公式得到的参数所设计的电路可以使SFQ脉冲在电路之间实现可靠传输.     

Bit error rate experiments in ring-shaped RSFQ circuits

Ring-shaped rapid single flux quantum (RSFQ) circuits composed of segments of Josephson transmission lines (JTLs) and other RSFQ circuits enable permanent SFQ pulse circulation. New ring structures of different designs have been realized which comprise T-flipflop (TFF) and multiplier (MULT) circuits. Reliability in circuit operation has been proven experimentally by a bit error rate BER≅10⁻¹⁶. The fabrication process has been optimized by using PTB-4 μm Nb/Al₂O₃–Al/Nb trilayer technology with externally shunted tunnel junctions of critical current densities of j_c=≅1 kA/cm². Characteristic voltage is V_c=250 μV and Steward–McCumber parameter β_c≤1. A linear dependence of pulse circulation frequency on JTL bias currents has been measured within a bias current interval of 20%.     

Widely Tunable Separate Absorption and Modulation Wavelength Converter With Integrated Microwave Termination

A widely tunable wavelength converter utilizing a separate absorption and modulation configuration and only dc bias connections is demonstrated. The device integrates an SG-DBR laser with a traveling-wave electroabsorption modulator and an optically pre-amplified receiver and introduces a simplified bias scheme by the inclusion of passive resistor and capacitor circuit elements. We discuss a the design of these passive elements and their compatibility with fabrication of photonic integrated circuits. The device demonstrates over 12 GHz optical bandwidth and error free 10 Gb/s wavelength conversion is achieved with less than 2.5 dB power penalty over 25 nm of output tuning.     

A dynamic line-termination circuit for multireceiver nets

In multidrop unterminated transmission line nets with one driver and many receiver circuits, the receiver located nearest to the driver switches last if it has to wait for the backward travelling wave reflected from the open end of the line. A lower driver impedance solves this problem but produces ringing due to multiple line reflections. In this paper, a dynamic termination circuit is presented that suppresses multiple reflections and ensures first incidence switching but does not have the power dissipation penalty incurred when a terminating resistor is used     

Sub-1-V swing internal bus architecture for future low-power ULSIs

A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-V_T MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3-μm processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization     

DC boosting effect of active bias circuits and its optimization for class-AB InGaP-GaAs HBT power amplifiers

In this paper, dc sourcing capability (DSC), which is a very important consideration in design of active bias circuits for power amplifiers based on bipolar technologies, will be explained. The nonlinear effect of bias circuits on the dc sourcing characteristics has been analyzed with simplified circuits for power amplifiers using the Volterra series. The analysis shows that the second-order distortion generated by a bias buffer transistor can boost bias level of the RF transistor to compensate finite DSC available in the absence of this effect. The bias-level boosting due to RF injection can be optimized by tuning the value of a series resistor between the emitter of the buffer transistor and the base of the RF transistor. Amplifiers with different series resistors have been implemented and tested with an IS95-B code-division multiple-access signal at the cellular band (824-849 MHz). The experimental results verify that a circuit-level optimization for the second-order distortion of the bias circuits is very important for optimizing the linearity and efficiency of the HBT amplifiers.     

Josephson edge-triggered gates for sequential circuits

A Josephson sequential logic family with a very wide operating margin (±67%) and insensitivity to global parameter variations is proposed. Derived from the original idea of the edge-triggered latching comparator by C. Hamilton et al. (see IEEE Trans Magnetics, vol.MAG-21, p.197-9, 1985), this logic gate consists of a pair of conventional gates in series biased by a delay clock. In normal operation, switching occurs in one and only one of the gates, depending on which one has the smaller critical current. The authors have built and tested a few circuits to illustrate this logic gate design: a 32-b shift register designed by OR gates with ±42% bias margin and ±89% input margin, a 4-b pseudorandom sequence generator designed by exclusive-OR gates with ±27% bias margin and ±78% input margin, and cross section of a 6-b NOR gate decoder with ±33% bias margin     

Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Due to the inevitable tradeoff between speed and breakdown voltage, the spectacular speed improvement of modern SiGe processes in recent history has partially been achieved at the cost of a reduction in breakdown voltages. Because supply voltages have hardly been reduced however, circuits operating at a supply voltage above the collector-emitter breakdown voltage (BV/sub CEO/) are common practice today and collector-base avalanche currents are therefore of major concern. Transistors that need to handle a collector-emitter voltage above (BV/sub CEO/) are typically found as output transistors in output driver stages and in bias current circuits. Such circuits can be designed to tolerate collector-emitter voltages above (BV/sub CEO/) by driving the base terminal with a relatively low impedance. This paper analyzes various conventional as well as two new bias current circuits supporting operation at collector voltages above (BV/sub CEO/). In the new circuits, feedforward and feedback avalanche current compensation techniques are introduced that obtain a substantial increase in output breakdown voltage of the bias circuits and improve the accuracy of the current mirror at output voltages above (BV/sub CEO/). With the feedback technique, a measured increase in output breakdown voltage by more than 2 V is demonstrated while the accuracy of the current mirror ratio at output voltages of 2 to 3 times (BV/sub CEO/) is improved by an order of magnitude.     

Phase-noise analysis of MEMS-based circuits and phase shifters

The effect of Brownian, acceleration, acoustic, and power-supply noise on MEMS based circuits has been calculated for MEMS.-based circuits (phase shifters, delay circuits). The calculations are done for capacitive shunt MEMS switches and metal-to-metal contact series MEMS switches. It is found that these effects result in both an amplitude and phase noise, with the phase noise being around 100× larger than the amplitude noise. The phase noise due to Brownian motion is negligible for MEMS switches with k ≃ 1.0 N/m, g₀ > 2 μm, Q > 0.5, and f₀ ≃ 50 kHz. The effect of acceleration and acoustic noise is negligible for a total acceleration noise of 10 g or less and a total acoustic noise of 74-dB sound pressure level. The power-supply noise depends on the bias conditions of the MEMS element, but is negligible for MEMS switches with a bias voltage of 0 V and a total noise voltage of 0.1 V or less. It is also found that metal-to-metal contact series switches result in much less phase noise than standard capacitive shunt switches. The phase noise increases rapidly for low spring-constant bridges (k = 0.24 N/m), low-height bridges, and bridges with a large mechanical damping (Q < 0.3). Also, varactor-based designs result in 30-40 dB more phase noise than switch-based circuits. This paper proves that microwave passive circuits built using MEMS switches (with a proper mechanical design) can be used in most commercial and military applications without any phase-noise penalty     

Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.     

Complementary Josephson junction devices and circuits: a possiblenew approach to superconducting electronics

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits     

A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits

Edge contact transistors are widely used in basic cells of gate-array circuits and custom designed circuits. The role of sheet and contact in affecting the performance of these transistors is investigated. A two-dimensional model has been developed to calculate the transistor's effective series resistance at various bias conditions. Very good correlation between the model and experiments has been obtained. It is found that different series resistances are observed in linear and saturation regions for edge contacts transistors in contrast to the conventional transistors. The results show that the effective series resistance of an edge contact transistor is nonuniform and is a complex function of the gate voltage, the drain voltage, and the linear or saturation bias conditions.     

High-temperature operation of oxide SFQ-circuit-elements

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.