基于改进型匹配网络的宽带高效率E类功放的设计

为了解决E类功放工作带宽过窄的问题,对E类功放的输入、输出匹配网络提出了一种改进方案.该方案中输出匹配网络采用微带线结构与切比雪夫低通匹配网络相结合的方法,在较宽的工作带宽内有效地抑制了谐波;并采用阻抗变换方法设计了含闭式解的宽带带通输入匹配网络,明显增强了输入匹配网络设计的灵活性.利用该方案,同时采用多谐波双向牵引技术得到功率管的最佳源阻抗和负载阻抗,基于CGH40010F功率管设计了一款应用于L波段的宽带高效率E类功放.测试结果表明,在输入功率为28dBm,漏极偏置电压VDS=28V,栅极电压VGS=-3.3V时,在整个L波段频率范围内漏极工作效率大于65%,最高达到83%,输出功率为39~41.1dBm,增益为11~13.1dB,增益平坦度为±1dB.这一结果验证了该改进方案的有效性,使得E类功放具有宽带宽、高效率的性能.     

30MHz-512MHz宽带功率放大器的研制

功率放大器是射频前端中的关键部件，宽带是目前功率放大器的主要发展趋势。根据宽带功率放大器的设计原理，采用推挽结构晶体管，前馈线性化技术，传输线变压器和微带混和匹配电路，利用ADS进行仿真设计，成功的设计出一款宽带功率放大器。实现了多倍频程带宽、确保带内增益平坦、驻波小、线性范围和动态范围大。通过仿真和测试，得到较为理想的结果。     

影响真空溅射用射频电源特性因素的研究

研究了用于真空溅射沉积射频电源的功率转换效率和频率稳定性的影响因素,分析了E类功率放大器和射频驱动级电路的工作特性。推演了最大输出功率公式,运用matlab对其归一化处理,得出最优占空比;在最优占空比条件下,根据射频电源功率放大器对射频驱动级电路的要求,设计了射频驱动级电路,提高了射频电源功率输出频率的稳定度。经电路实验测试,其结果显示,波形规整、稳定。     

高效率基站功放的研究与设计

对称Doherty结构功率放大器在功率回退6dB的时候有较高的效率。用两个不同功率的LDMOSFET晶体管设计可用于TD-SCDMA基站的非对称Doherty功率放大器。当回退功率为10dB时,整个系统效率为46%,仍保持较高的效率,实现小功率下的高效率。峰值功率为主功放功率的两倍,总的最大输出功率为110W。     

250WD类晶体管功率放大器

本文以实用电路为例,介绍了中等功率D类晶体管功率放大器的设计、电路特点及调试方法。     

功放与扬声器系统的配接（二）

5.音频功率的传输功率放大器的功率传输,有低阻抗定阻功率传输和高阻抗定压功率传输两种方式。(1)低阻抗定阻功率传输低阻抗定阻功率传输属于功率匹配输出状态,理论上,要求功率放大器的负载阻抗严格等于功率放大器输出级电路负载线的斜率,此时,输出电路处于最佳的设计状态,信号的摆动范围充分利用了功率放大器输出晶体管的线性化区域,功率转换效率最高,即电源利用效率最大,此时,输出功率最大,动态范围最大,失真最小,频响最宽。一个性能优秀的功率放大器,在低阻输出的要求下,放大器能适应一个低阻负载的范围,除能适应标准的8?Ω扬声器系统之…     

基于ADS的5mm波二倍频器的设计与仿真

采用商用的变容二极管MA46H146,利用ADS软件,通过拟合其C-V曲线,研制一款5mm波串联单管二倍频器,该二倍频器在输入功率5dBm时、直流偏压1.2V时,二次谐波输出2.923dBm,效率为61.99%。     

D类功率放大器的设计

本系统以高效率D类功率放大器为核心,输出开关管采用高速VMOSFET管,连接成互补对称H桥式结构,最大不失真输出功率大于1W,平均效率可达到70%左右,兼有输出1:1双变单电路,此外还有输出短路保护及指示、输出音量电平指示等辅助功能,比较理想地实现了设计指标的要求。     

米波段10W功率放大器的ADS仿真设计

功率放大器是发射机非常关键的部件,广泛应用于通信、雷达等微波系统,其性能将影响整个系统的技术指标,因此微波功率放大器的设计成了微波发射系统的关键。现阶段,米波段雷达的应用越来越广,米波段功率放大器的需求也逐渐增多。介绍利用ADS设计米波段功率放大器的详细过程,并给出量终的实物测试结果,输出功率>10W,增益平坦度<0.5dB,效率>50%,仿真设计结果和实测结果基本一致。     

用于TMA的平衡式低噪声放大器设计

针对通信基站中塔顶放大器的应用,设计了一种应用于TMA的平衡式低噪声放大器,放大器采用平衡式放大器技术和微型3dB混合耦合器,提高了放大器的性能指标,显著减小了电路尺寸,在确定放大器直流工作点后进行输入端和输出端阻抗匹配,给出了版图设计和仿真结果,利用ADS联合仿真功能,得出了一个比原理图仿真更接近实际电路的结果,仿真结果表明在800～1000MHz的频率范围内,噪声系数不大于1dB,功率增益达到15dB左右,输入输出驻波比小于1.2。     

Analysis of a class E power amplifier with series-parallel resonator

The authors propose new class E power amplifier configuration with an equivalent series-parallel resonator network. The boundary conditions for the 100% efficiency operations are analysed under the conditions that the duty ratio is 0.5 and the loaded quality factor is infinite. If the DC supply voltage and the output power are assumed the same, the load resistance R is 53.65% higher, the excess series inductance L/sub x/is 3.99% lower and the maximum frequency f/sub max/is improved by 6.47% compared with the conventional class E amplifier. The theoretical analysis is verified by numerical results and harmonic balance simulations. And a lumped element test board is built and measured at 200 MHz utilising a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) transistor MRF21010 as the switching device. An output power of 33.03 dBm, a drain efficiency of 85.6% and a gain of 16 dB are measured. The approximate transmission-line topology with harmonics suppression is also proposed.     

A High Gain,Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.     

A High Gain,Noise Cancelling 2515-4900 MHz CMOS LNA for China Mobile 5G Communication Application

With the development of the times, people’s requirements for communication technology are becoming higher and higher. 4G communication technology has been unable to meet development needs, and 5G communication technology has emerged as the times require. This article proposes the design of a low-noise amplifier (LNA) that will be used in the 5G band of China Mobile Communications. A low noise amplifier for mobile 5G communication is designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 μm Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) process. The LNA employs self-cascode devices in currentreuse configuration to enable lower supply voltage operation without compromising the gain. This design uses an active feedback amplifier to achieve input impedance matching, avoiding the introduction of resistive negative feedback to reduce gain. A common source (CS) amplifier is used as the input of the low noise amplifier. In order to achieve the low power consumption of LNA, current reuse technology is used to reduce power consumption. Noise cancellation techniques are used to eliminate noise. The simulation results in a maximum power gain of 22.783, the reverse isolation (S₁₂) less than -48.092 dB, noise figure (NF) less than 1.878 dB, minimum noise figure (NFmin)=1.203 dB, input return loss (S₁₁) and output return loss (S₂₂) are both less than -14.933 dB in the frequency range of 2515-4900 MHz. The proposed Ultra-wideband (UWB) LNA consumed 1.424 mW without buffer from a 1.2 V power supply.     

2.4 GHz Class-E power amplifier with transmission-line harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%     

Research on cryogenic behaviors of low noise amplifier with build-in PIN diode limiter

In this article we elucidate the design and fabrication of a P-band cryogenic low noise amplifier (CLNA) with built-in limiter circuit, and further studied the characteristics of PIN diode limiter at different temperature. Measurements at 75 K shows the P-band CLNA with build-in limiter has a good performance with noise figure lower than 0.5 dB, the input and output voltage standing wave ratio (VSWR) less than 1.5 and input 1 dB power compression point ?4 dBm within the band width 300 MHz. The variation of the gain within ±0.1 dB under the impact of 20 dBm input power level signals. In addition, the maximum allowed input power of the CLNA has increased from 13 dBm to 22 dBm.     

5.25 GHz CMOS cascode power amplifier for 802.11a wireless local area network

The authors investigate a 5.25 GHz highly integrated CMOS class-AB power amplifier for IEEE 802.11a wireless local area network. The proposed power amplifier is implemented with a two gain-stage structure which is followed by an off-chip output matching circuit. Moreover, transistor-level compensation techniques are employed to improve the linearity. The power amplifier is designed with an on-chip input matching circuit, whereas the output matching circuit translates the signal power from 50 to 20 V load resistance. The measured results indicate over 20% power-added efficiency, over 20 dBm output power and 28.6 dBm output IP3. All the specifications are based on 50 V input impedance at 2.4 V supply voltage.     

一种用于多标准接收机的宽带低噪声放大器

设计了一种应用于软件无线电接收机的300kHz～1.6GHz宽带低噪声放大器,适用于数字广播、数字电视和定位导航等系统.该放大器采用噪声抵消结构以降低输入匹配器件在输出端所产生的热噪声和闪烁噪声,能够同时实现输入阻抗匹配和噪声优化.对采用中芯国际(SMIC)0.18 μm RF CMOS工艺实现的芯片的测试结果表明,3dB带宽为300kHz～1.6GHz,最大增益S21为16.7dB,输入反射系数S11小于-7.4dB,最小噪声系数为2.3 dB,输入参考的1dB增益压缩点为-11.6dBm,功耗为14.4mW,芯片面积为0.49mm2.     

一种全桥式高功率放大器

用集成功率放大器驱动大功率三极管构成推挽功率放大器,两路推挽功率放大单元可以组合构成全桥式功率放大器,这种放大器大量使用大功率三极管等分立元件,能够提高电路总的额定功率,并且使元件布局分散有利于实现散热设计,工程样机研制证明该方法适用。水库测试结果表明:驱动某大型双谐振压电陶瓷换能器,功放样机输出连续信号时,在5 k Hz左右输出电功率达到1600 W以上。单频信号工作时观察信号波形,信号畸变与失真较小。根据试验与测试结果分析了末级三极管上的功率耗散情况,验证了工程样机在散热设计方面的有效性。