Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

Ti-Si-N diffusion barriers between silicon and copper

Thin films of Ti-Si-N, reactively spattered from a Ti₅Si₃ target, are assessed as diffusion barriers between silicon substrates and copper overlayers. By tests on shallow-junction diodes, a 100 nm Ti₃₄Si₂₃N₄₃ barrier is able to prevent copper from reaching the silicon substrate during a 850°C/30 min anneal in vacuum. A 10 nm film prevents diffusion up to 650°C/30 min. By high-resolution transmission electron microscopy, Ti₃₄Si₂₃N₄₃ predominantly consists of nanophase TiN grains roughly 2 nm in size     

The effect of Cu diffusion on the TDDB behavior in a low-k interlevel dielectrics

The effect of Copper on TDDB failure in a structure incorporating a low-k interlevel dielectric was studied theoretically and experimentally. Interdigitated comb capacitor structures were prepared with and without Cu metallization and stressed at 4.0 to 6.6 MV/cm at 150C. The samples without Cu did not fail to over 1800 hours at 4 MV/cm whereas the samples with Cu exhibited a median time to failure (t₅₀) of 45 minutes. At 6.6 MV/cm, the t₅₀ was 1.8 hours for the Cu free samples. This experiment demonstrated the importance of Cu in the TDDB behaviour of low-k dielectrics, but also demonstrated that the presence of Cu was not a necessary condition for failure. The effect of Cu diffusion on TDDB behaviour was studied in the context of the “Impact Damage” model. Both field assisted ionic diffusion and diffusion of neutral Cu was considered. It is seen that the behaviour at low fields near use conditions may have little relationship to the predictions obtained from the results of typical TDDB testing.     

TaN-TiN binary alloys and superlattices as diffusion barriers for copper interconnects

Binary alloys and superlattices of TaN-TiN thin films were grown on Si(100) substrates with a TiN buffer layer using pulsed laser deposition. A special target assembly was used to manipulate the concentrations of these binary component films. The 60% TaN resulted in a TaN (3 nm)/TiN (2 nm) superlattice, while 30% and 70% TaN generated uniform Ta_xTi_1−xN alloys. X-ray diffraction (XRD), transmission electron microscopy (TEM), and scanning transmission electron microscopy (STEM) confirmed the single-crystalline nature of these films. Four-point probe resistivity measurements suggest that these alloy and superlattice films have a lower resistivity than pure single-crystalline TaN films. The Cu-diffusion characteristic studies showed that these materials would have the potential as high-temperature diffusion barriers for Cu in ultra-large-scale integration technology.     

Thermal stability and gap-fill properties of spin-on MSQ low-k dielectrics

Looking onto integration of low-k materials within FEOL used processing temperatures in this field are much higher than within BEOL. In addition partly high aspect ratio features have to be filled without defects, e.g. within usage of spin-on low-k materials for shallow trench isolation. We evaluated two MSQ-based spin-on dielectrics, a porous ultralow-k material and a dense spin-on glass regarding their thermal stability and gap-fill behaviour. The films were annealed from standard curing temperatures up to temperatures of 850 °C and 900 °C, film thickness and refractive index were measured by spectral ellipsometry, electrical film properties were evaluated by a mercury probe measurement and changes within chemistry are studied by FTIR. Both low-k materials are thermally stable up to temperatures of 650-700 °C. Above this range the film thickness is rapidly decreasing, refractive index and corresponding to that the k-value are strongly increasing, as does the leakage current density. FTIR spectra show a shift within Si-O-Si backbone and Si-CH₃ and CH₃ bonds are vanishing, while OH groups are adsorbed, additionally leading to higher k-value and leakage currents. Both materials show very good gap-fill properties, filling features with aspect ratios up to 5 or 10 and Aluminium covered structures without any visible defects.     

Influence of low-k dry etch chemistries on the properties of copper and a Ta-based diffusion barrier

In this study, the film properties of Cu and a Ta-based diffusion barrier deposited on organic polymer and SSQ-based low-k materials with subtractive porosity were investigated. Emphasis was put on the effects of exposure of the low-k materials to the dry etch plasmas prior to metal deposition. The metal film properties were influenced by the type of the dry etch plasma chemistry used and by the porosity of the low-k material. Thermal desorption spectra (TDS) obtained during annealing of these metal films revealed an increased amount of species with m/e 44, attributed to CO₂, and H₂O desorbing from the Cu film at high temperatures. The TDS data for the Ta film did not contain such high temperature desorption peaks for these species mentioned. Surface morphology of the Cu and Ta films observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM) also showed a poor wetting of the metal films on the porous low-k materials that have been dry etch plasma treated.     

Reliability issues for nano-scale CMOS dielectrics

Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues, new materials as metal gates and high-k gate dielectrics have been integrated. These new materials require that we gain understanding of the reliability physics related to these new materials (such as Vt instability, gate oxide breakdown) and that we develop high confidence-level design rules.     

Improved compact thermal model for studying 3-D interconnect structures with low-k dielectrics

Compact thermal modeling is gaining significance as interconnect feature sizes continue to shrink, requiring increased computation times for full-field multi-scale simulations. Improved and expanded uses of an existing compact thermal modeling approach found in Gurrum et al. [A compact approach to on-chip interconnect heat conduction modeling using the finite element method, ASME J. Electron. Packaging (2007), accepted], Gurrum et al. [A novel compact method for thermal modeling of on-chip interconnects based on the finite element method, ASME, EEP 3, Electron. Photon. Packing Electr. Syst. Photon. Des. Nanotechnol. (2003) 441-445] are presented here. The first improvement rectifies a singularity that occurs in the previous compact model. This change allows for greater flexibility in mesh application, and a greater number of structures that can be analyzed. This work focuses on the application of the compact thermal model to two interconnect structures. The first geometry [S. Im, N. Srivastava, K. Banerjee, K. Goodson, Scaling analysis of multilevel interconnect temperatures for high performance ICS, IEEE Trans. Electron. Dev. 52 (12) (2005) 2710-2719] is a typical interconnect structure based on the ITRS 65 nm technology node. A new transient compact model was applied to another geometry [J. Zhang, M. Bloomfield, J. Lu, R. Gutmann, T. Cale, Thermal stresses in 3D IC inter-wafer interconnects, Microelectron. Eng. 82 (3-4) (2005) 534-547], which is a more advanced technology with a through-the-die via structure. The second improvement of the compact model is extending the steady state finite element based model into a transient version. Full-field simulations have very large storage and memory requirements for transient analysis of complex structures. The advantage of this compact model is that in addition to increased efficiency, the methodology and implementation is similar to a traditional finite element analysis (FEA).     

Crystallization and failure behavior of Ta-Ni nanostructured/amorphous diffusion barriers for copper metallization

This work examines the thin-film properties and diffusion barrier behavior of sputtered Ta-Ni films, aiming at depositing highly crystallization-resistant and conductive diffusion barriers for Cu metallization. Structural analysis indicates that the as-deposited Ta-Ni films indeed have a glassy structure and are free from highly resistive intermetallic compounds. Examining Si/Ta-Ni/Cu stacked samples reveals that thermally induced failure of amorphous Ta-Ni barriers is triggered by the barrier’s reaction with the silicon substrate at temperatures around 700°C. The effectiveness of the amorphous Ta-Ni thin film thus can be substantially enhanced by effectively blocking diffusion of copper toward the underlying silicon.     

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10 nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using I_leak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced E_OX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.     

The evolution of optical and electrical properties of low-k dielectrics under bias stress

Photocurrent spectroscopy and transient photocurrent measurements are employed in order to investigate the change in barrier heights and density of traps within low-k dielectric films under bias stressing conditions. By characterizing these fundamental physical properties, we hope to gain an understanding of the processes leading to time-dependent dielectric breakdown.     

倒装焊器件中Cu/low-k结构热可靠性分析

利用有限元软件建立了倒装焊器件的整体模型和Cu/low-k结构的子模型,分析了在固化工艺及后续热循环条件下Cu/low-k结构的热机械可靠性。结果表明:在金属互连线与低电介质材料的交界处容易产生可靠性问题,采用low-k材料及铜互连线时均增大了两者所受最大等效应力,另外,通孔宽度对low-k及铜线的热应力影响并不明显。     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

Reliability challenges for deep submicron interconnects

Deep submicron interconnects (leads, contacts and vias) are rapidly becoming one of the major reliability challenges as ULSI devices continue to be scaled. With 0.5um feature sizes now common, trying to balance reliability and performance requirements is increasing difficult as we move toward <0.25um. By the end of the decade, current density in metal leads will be >0.5 Ma/cm2 and single 0.20–0.25um contacts and vias will be required to safely carry 1–2ma of current. This increases electromigration concerns, with vias generally now being the weakest link in a reliable ULSI multilevel-metal system.     

Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.