Performance of ITU-T G.729 8 kb/s CS-ACELP speech codec withnonvoice narrowband signals

A report is given on the results of a series of objective measurements conducted by COMSAT in a laboratory environment aimed at characterizing the narrowband performance of the ITU-T G.729 8 kb/s conjugate-structure algebraic code-excited linear prediction (CS-ACELP) speech coder. The test procedures followed ITU-T Recommendation G.720, “Characterization of Low-Rate Voice Coder Performance with Non-Voice Signals”. It was concluded that the G.729 algorithm has excellent performance with narrowband signals in general (e.g., single tones and DTMF signals). As for Signaling System No. 5 (SS5) interregister signals, the G.729 CS-ACELP frequently failed to correctly identify SS5 digit 6 in a number of occurrences, using worst-case analysis equipment. This indicates that the SS5 performance of G.729 codecs in trunks where SS5 is used should be carefully measured before the network planner decides on its deployment. Great care should also be taken for tandem connections, since no test has been performed for these configurations     

Characterizing the subjective performance of the ITU-T 8 kb/sspeech coding algorithm-ITU-T G.729

Three listening-only experiments were conducted to characterize the subjective performance (i.e., speech quality) of 8 kb/s G.729. These experiments evaluated the quality of coded speech under a variety of conditions: (i) interworking with other international and regional speech coding standards; (ii) input speech that had been corrupted by environmental noise; (iii) operation over degraded transmission channels (including random bit errors and a simulated radio channel). The results of these experiments indicate that 8 kb/s G.729 meets the performance requirements that were established at the beginning of the standardization process     

基于GMM的AMR-NB与G.729A之间的LSP参数转码方法

通过对高斯混合模型的数学分析,建立并实现了一种基于高斯混合模型的、AMR-NB与G.729A之间的LSP参数转码算法,并通过实验对高斯混合模型在转码中的一些实际应用问题进行了分析和讨论.实验结果表明,提出的基于高斯混合模型的LSP参数转码算法在合成语音质量不次于DTE方法的同时,LSP参数转码复杂度下降了78%以上.     

The road to G.729: ITU 8-kb/s speech coding algorithm with wirelinequality

In November 1995 the International Telecommunication Union Telecommunications Sector (ITU-T) approved an 8-kb/s speech coding algorithm with wireline quality. This culminated the effort that the CCITT had set in motion in 1990. This article presents the methods for managing the project through its major milestones from setting the terms of reference to the selection, testing, optimization, and dissemination of the algorithm. While G.729 was being finalized, a new requirement for a low complexity 8-b/s speech coding arose. This article explains how the change in scope was accommodated without the unnecessary proliferation of incompatible algorithms     

3GPP AMR—NB与ITU—TG．729A语音编码标准技术的对比研究

介绍了AMR—NB与G．729A2种语音编码标准的特点和算法,并就其线性预测分析、基音搜索、代数码书搜索和增益量化4个方面技术进行了比较。在线性预测分析方面主要对2种算法的加窗、LSP量化与内插的不同进行了陈述;在基音搜索方面对开环和闭环基音搜索上的差异进行了分析,并且对代数码书结构和搜索算法及增益参数量化的差别进行了阐述。最后给出了2种编码标准的语音质量、计算复杂度、空间复杂度等性能测试结果。     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

母亲还原叶酸载体1基因80G/A多态性与子女唐氏综合症易感性关系的meta分析

目的:探讨母亲还原叶酸载体1(RFC1)基因80G/A多态性与子女唐氏综合症(DS)易感性的相关性.方法:计算机检索PubMed、MEDLINE 、Web of Science、CNKI、CBM数据库,收集从建库至2012年9月间关于母亲RFC1基因80G/A多态性与子女DS易感性相关性的病例对照研究,对符合纳入标准的文献进行Meta分析.结果:共纳入7个研究,包括病例625例,对照767例.Meta分析结果显示:母亲RFC1基因80G/A多态性与子女DS易感性的相关性在各比较模型中差异无统计学意义[A Vs.G:OR=0.85,95％CI(0.73,1.00);AA Vs.GG:OR=0.73,95％CI(0.53,0.99)；AA Vs.AG+ GG:OR=0.82,95％CI(0.63,1.06)；AA+ AG Vs.GG:OR=0.81,95％CI(0.64,1.03)].基于人种的亚组分析结果显示,两者相关性无统计学意义.结论:目前的研究结果显示,母亲RFC1基因80G/A多态性与子女DS易感性无明显相关性.     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

40-Gb/s systems on G.652 fibers: comparison between periodic and all-at-the-end dispersion compensation

In the literature, two system solutions have been proposed to overcome high dispersion problems typical of G.652 fibers at high bit rates (40 Gb/s): they are periodic and all-at-the-end dispersion compensation. We carry out an exhaustive comparison between the two methods that, up to this moment, have been studied separately. In the first part, we introduce a simplified model on strong dispersion management (DM) with intrachannel four-waves mixing (IFWM) and intrachannel cross-phase modulation (IXPM). We then carry out extensive numerical simulations of a complete system in order to verify the results as a function of the input average power and of the input pulsewidth. Finally, we tackle a typical system aspect, i.e., the influence of nonlinear effects on dispersion compensating fibers (DCFs).     

A fully integrated 40-Gb/s clock and data recovery IC with 1:4DEMUX in SiGe technology

In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors' best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10^-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10^-10 requires an optical signal-to-noise ratio of 23.3 dB     

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology

A fully integrated OC-768 clock and data recovery IC with SFI-5 1:16 demultiplexer is designed in a 120-GHz/100-GHz (f/sub T//f/sub MAX/) SiGe technology. The 16 2.5-Gb/s outputs and additional deskew channel are compliant with the Serdes Framer Implementation Agreement Level 5 specification. The measured bit-error rate is <10/sup -15/. The measured jitter tolerance exceeds the mask specified in G.8251. The IC operates with 1.8-V and -5.2-V supplies and dissipates 7.5 W.     

A co-designed coding,modulation and equalization scheme for the transmission of 155-52 Mbit/s data over a 72 MHz intelsat transponder. Part 2: Equalization

This paper reports on the application of co-designed coding, modulation and equalization techiques to an INTELSAT requirement for transmitting 155-52 Mbit/s data over a 72 MHz satellite channel. A specific solution as regards coding, modulation and equalization is proposed and analysed that differs from ‘standard’ concatenation in that the inner decoder integrates equalization, modulation and coding. In Part 2, a novel technique for integrating decision feedback equalization into the inner decoder is described. The gains in integrating the coding and equalization are shown to be significant for channels that need equalizing.     

A co-designed coding,modulation and equalization scheme for the transmission of 155-52 Mbit/s data over a 72 MHz intelsat transponder. Part 1: Coding and modulation performance

This paper reports on the application of co-designed coding, modulation and equalization techniques to an INTELSAT requirement for transmitting 155-52 Mbit/s data over a 72 MHz satellite channel. A specific solution as regards coding, modulation and equalization is proposed and analysed that differs from ‘standard’ concatenation in that the inner decoder integrates equalization, modulation and coding. In Part 1 results of extensive computer simulations are presented, examining the effect of adjacent channel interference, co-channel interference, non-linear distortion in representative ground and space TWTAs, multiplexers and filter distortion. In Part 2 a novel technique for integrating decision feedback equalization into the inner decoder is described. The gains in integrating the coding and equalization are shown to be significant for channels that need equalizing.