A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer

A second-order multibit bandpass /spl Sigma//spl Delta/ modulator (BP/spl Sigma//spl Delta/M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP/spl Sigma//spl Delta/M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-/spl mu/m CMOS technology, the device die size is 1 mm/sup 2/ and the power consumption is 88 mW. In production, the BP/spl Sigma//spl Delta/M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is -65 dBc for two tones at -11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP/spl Sigma//spl Delta/M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

A design is presented for an 8-bit/spl times/8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-/spl mu/m CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated.     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.     

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.     

A Spur Elimination Technique for Phase Interpolation-Based Fractional-$N$ PLLs

A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-$N$ phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional- $N$ PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented.      

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-/spl mu/m CMOS

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process

A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Q/sub max/) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A precise 90/spl deg/ quadrature OTA-C oscillator tunable in the 50-130-MHz range

We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-/spl mu/m CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.     

Wideband L-probe-feed patch antenna with dual-band operation forGSM/PCS base stations

A dual-band microstrip composed of two patches and two L-probes is proposed. The antenna displays wide-bandwidth characteristics and can be implemented as a dual-mode GSM/PCS base station antenna     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

In this paper a 2-/spl mu/m CMOS, microprogrammable Signal Processor Core (SPC) is described,intended as the number crunching unit in single-chip general purpose digital signal processors. This core contains a 16 X 16 bit paralleI multiplier, a 40-bit multiprecision accumulator, a 40--32-bit extractor, an overflow detection unit, a format adjuster, and a three-port register file for local storage of 15 operands. Its 100-ns throughput rate makes it highly suitable for signal processing systems with sample rates up to 50 kHz (speech, telecom, and HiFi audio). The architecture of this unit is discussed in detail.The design approach, using full-custom cells, bit-sliced functional blocks, and a complete bottom-up logical verification of mask data, is also discribed. The Signal Processor Core contains 19 200 transistors on a 15.5-mm/sup 2/ area. This compares with a packing density of 1200 transistors/mm/sup 2/.     

Thermo-optical modulation at /spl lambda/=1.5 /spl mu/m in an /spl alpha/-SiC-/spl alpha/-Si-/spl alpha/-SiC planar guided-wave structure

A planar waveguide based on an amorphous silicon-amorphous silicon carbide heterostructure is proposed for the realization of passive and active optical components at the wavelengths /spl lambda/=1.3-1.5 /spl mu/m. The waveguide has been realized by low temperature plasma enhanced chemical vapor deposition and is compatible with the standard microelectronic technologies. Thermo-optical induced modulation at /spl lambda/=1.5 /spl mu/m is demonstrated in this waveguide. Numerical simulations predict that operation frequencies of about 3 MHz are possible. The measurements have also allowed the determination of the previously unknown thermo-optical coefficient of undoped amorphous silicon at this wavelength.