Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

多阈值神经元电路设计及在多值逻辑中的应用

分析了多阈值神经元工作原理,并提出设计多阈值神经元电路的方法．首先,用两个MOS晶体管组成电压型突触电路,然后又提出一种基于BiCMOS工艺的判别转换开关电路,这种电路以压控电流作为阈值信号,并实现电压到电流的转换．在此基础上,结合限幅电压开关理论提出多阈值神经元阈值判别函数电路的开关级设计方法．最后,从开关级设计了实现三值逻辑中文字、与、或三种基本运算的多阈值神经元电路,用这三种基本运算的多阈值神经元电路可实现任意三值函数的多阈值神经网络．文章还对设计出的电路用PSPICE进行模拟,测量相关参数．模拟结果表明,该文设计的电路不仅实现了正确的逻辑功能,而且速度较快。     

低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。     

Design and analysis of carbon nanotube FET based quaternary full adders

CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.     

应用输入向量控制技术降低漏电功耗的快速算法

随着工艺的发展,为保证电路的性能和噪声容限必须降低阈值电压,这将导致漏电流呈指数增长,漏电功耗因而将逐渐超过动态功耗占据主导地位.CMOS的堆栈效应导致电路在不同向量下的静态功耗不同,因此在电路进入睡眠状态时使用输入向量控制技术是一种低功耗设计的有效方法,如何快速找到一个可降低电路漏电功耗的向量就成了问题的关键.介绍了一种在给定向量集合中查找低功耗向量的快速算法--基于概率传递的标记算法,并为此开发了一个事件驱动的门级组合电路仿真器.通过对ISCAS和龙芯处理器电路的实验结果表明,该算法同传统方法比较可以提高性能3.4倍,误差率仅约0.14%.     

基于自适应并联电感同步开关控制的压电能量俘获电路设计

并联电感同步开关（P-SSHI）电路可以提高压电能量俘获能力,但其能量俘获效率受到开关控制精准性、整流电路导通压降等因素的影响。因此,本文提出了一种将超低压降有源整流与自适应P-SSHI结构相结合的高效压电能量俘获电路。其中,超低压降有源整流的上半桥采用交叉耦合被动开关的PMOS对管结构,下半桥则采用有源电路控制开关的NMOS对管结构,从而有效地降低了整流电路的导通压降。为进一步提高电路的压电俘获效率,本文采用自适应同步开关控制的P-SSHI结构以提高开关控制的精准性。该结构通过对整流电路中的电流进行过零检测确定同步开关的闭合时刻,对L-C振荡回路中的电流进行过零检测确定同步开关的断开时刻。实验结果表明,所提电路可以实现同步开关的自适应控制,并可有效提高压电能量俘获电路的整体效率。与全桥整流电路相比,本文所提电路可将输出功率提高到235%。     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage, SPICE measurements showed up to 45% improvement in the power delay product.     

A real-time QoE methodology for AMR codec voice in mobile network

This paper studies a general strategy to predict voice Quality of Experience （QoE） for various mobile networks. Particularly, based on data-mining for Adaptive Multi-Rate （AMR） codec voice, a novel QoE assessment methodology is proposed. The proposed algorithm consists of two parts. The first part is devoted to assessing speech quality of fixed rate codec mode （CM） of AMR while in the other one a adaptive rate CM is designed. Measuring basic network parameters that have much impact on speech quality, QoE can be monitored in rei time for operators. Meanwhile, based on the measurement data sets from real mobile network, the QoE prediction strategy can be implemented and QoE assessment model for AMR codec voice is trained and tested. Finally, the numerical results suggest that the correlation coefficient between predicted values and true values is greater than 90~0 and root mean squared error is less than 0.5 for fixed and adaptive rate CM.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

A CMOS low noise amplifier based on common source technique for ISM band application

In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ?9.14, ?9.22 and ?38.03 dB respectively. The 1 dB compression point of the circuit is ?16.89 dBm and IIP3 is ?5.70 dBm. The noise figure is 2.34 dB, input/output match of ?9.14 dB/?9.22 dB and power consumption 8.5 mW at 1.2 V.     

Simple pixel circuits for high resolution and high image quality organic light emitting diode‐on‐silicon microdisplays with wide data voltage range

Two simple pixel circuits are proposed for high resolution and high image quality organic light‐emitting diode‐on‐silicon microdisplays. The proposed pixel circuits achieve high resolution due to simple pixel structure comprising three n‐type MOSFETs and one storage capacitor, which are integrated into a unit subpixel area of 3 × 9 µm² using a 90 nm CMOS process. The proposed pixel circuits improve image quality by compensating for the threshold voltage variation of the driving transistors and extending the data voltage range. To verify the performance of the proposed pixel circuits, the emission currents of 24 pixel circuits are measured. The measured emission current deviation error of the proposed pixel circuits A and B ranges from ?2.59% to +2.78%, and from ?1.86% to +1.84%, respectively, which are improved from the emission current deviation error of the conventional current‐source type pixel circuit when the threshold voltage variation is not compensated for, which ranges from ?14.87% to +14.67%. In addition, the data voltage ranges of the proposed pixel circuits A and B are 1.193 V and 1.792 V, respectively, which are 2.38 and 3.57 times wider than the data voltage range of the conventional current‐source type pixel circuit of 0.501 V.     

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation.Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor(CMOS)circuits during test has become a significant part of the total power dissipation.Hence,it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test,to increase test reliability and to reduce test cost.This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it,we propose techniques based on don't care bits(denoted by Xs)in test vectors to optimize leakage current in integrated circuit(IC)test by genetic algorithm.The techniques identify a set of don't care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector(MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.     

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic （ICPAL） based on fin-type field- effect transistor （FinFET） devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies（30-800 MHz） under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass- transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.     

一种改进的串联电池组单体电池电压测量方法

针对基于运算放大器和MOSFET管的串联电池组单体电池电压测量方法存在漏电流的问题,提出了一种改进的电压测量方法。在每节电池的两端增加了一个电压跟随器,可有效降低漏电流;增加了光电继电器作为运算放大器的电源开关,使电压测量电路在断电状态下不消耗电流;增加了一个稳压二极管,以防止MOSFET管被击穿。测试结果验证了改进方法的有效性。     

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Based on the drift-diffusion theory, a simple threshold voltage and drain current model for symmetric dual-gate (DG) amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is developed. In the subthreshold region, most of the free electrons are captured by trap states in the bandgap of a-IGZO, thus the ionized trap states are the main contributor to the diffusion component of device drain current. Whereas in the above-threshold region, most of the trap states are ionized, and free electrons increase dramatically with gate voltage, which in turn become the main source of the drift component of device drain current. Therefore, threshold voltage of DG a-IGZO TFTs is defined as the gate voltage where the diffusion component of drain current equals the drift one, which can be determined with physical parameters of a-IGZO. The developed threshold voltage model is proved to be consistent with trap-limited conduction mechanism prevailing in a-IGZO, with the effect of drain bias being also taken into account. The gate overdrive voltage-dependent mobility is well modeled by the derived threshold voltage, and comparisons of the obtained drain current with experiment data show good verification of our model.     

基于电流控制模式的低压、高PSRR基准源

基于可调电流控制模式设计出一种低压、高电源抑制比的带隙基准电压源电路。采用电流控制模式和多反馈环路,提高电路的整体电源抑制比;通过电阻分压的方式,使电路达到低压,同时提供偏压,简化偏置电路。采用0.5μmCMOS N阱工艺,电路可在电源电压为1.5V时正常工作。使用Cadence Spectre进行仿真结果表明,低频时电源抑制比(PSRR)高达107dB。-10℃～125℃温度范围内,平均温度系数约7.17ppm/℃,功耗仅为0.525mW。此电路能有效地抑制制程变异。