32位同时多线程微处理器的ALU设计

针对传统ALU存在较大硬件资源浪费的缺点,提出了一种指令执行并行度宽,资源利用率高的同时多线程ALU.同时多线程ALU由7个并行的部件组成.每个部件高效的执行两个线程的指令.这种由7个部分组成的分布式ALU提高了指令并行执行的宽度,大大降低了水平浪费和垂直浪费.对微处理器ALU进行功能验证与仿真,并用综合工具完成逻辑综合.     

8位微控制器体系架构的设计研究

本文分析了目前8位微控制器的更新和设计趋势,主要讨论其RISC体系架构的产品设计,并重点从体系架构的角度出发,就高性能、低功耗两方面对在设计中采用的关键技术进行了探讨研究.     

Label-free detection of DNA hybridization using gold-coated tapered fiber optic biosensors (TFOBS) in a flow cell at 1310 nm and 1550 nm

We had previously reported the detection of a model protein bovine serum albumin (BSA) using antibody-immobilized tapered fiber optic biosensors (TFOBS) at 1310 nm and 1550 nm under stagnant and flow conditions. Because of recent interest in pathogen detection based on DNA, in this work we explore the application of these sensors for the detection of single stranded DNA (ssDNA). We show that it is feasible to directly detect the hybridization of a 10-mer ssDNA to its complementary strand immobilized on the sensor surface. Detection was performed under flow conditions because flow reduces non-specific binding to sensor surface, eliminates optical transmission changes due to mechanical movements, and allows for instantaneous switching of samples when needed.

TFOBS were fabricated with waist diameters of 5–10 μm and total lengths of 1000–1200 μm. The taper regions were coated with 50 nm of gold and housed in a specially constructed holder which served as a flow cell. The TFOBS was immobilized with 15-mer ssDNA with a C₆ extension and a thiol group, which attaches to Au1 1 1 sites. Then, the complementary 10-mer ssDNA samples were allowed to flow in from low to high concentration (750 fM to 7.5 nM) and the resulting transmission changes were recorded. It is shown that 750 fM of complementary DNA can be detected. This sensor was able to distinguish between complementary DNA from DNA with a single nucleotide mismatch in the middle position.     

Design and testing of a reversible ALU by quantum cells automata electro-spin technology

The Journal of Supercomputing - Arithmetic logic unit (ALU), a core component of a processor, is one of the thrust areas of the current research. Presently, ALU is designed by transistor-based CMOS...     

8位LVDS串行器的设计研究

这篇论文主要分析了用于高速数据传输的LVDS技术以及该技术常用的一个接口电路-串行器。它主要包括一个LVDS驱动器、并串转换器、以及产生多相时钟的锁相环电路．本文重点介绍了一种能够实现高速转换的并串转换器，这个串行器的数据转换速率达到了250Mbyte／s，并且其传输速度达到了2Gbps。     

GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45 nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.     

基于RISC技术的8位微控制器设计

介绍基于RISC技术的8位微控制器的设计与实现。主要包括RISC指令集的选取;取指单元、译码单元、执行单元的设计;取指、译码、回写三级流水线技术的实现。该微控制器包含8级硬件堆栈、1个8位计数器、1个计数器溢出中断、2个外部中断源、8位数据输入和输出端口、16个通用寄存器、2K×16位的程序存储器、512字节的数据存储器。设计使用可综合的Verilog语言描述,QuartusⅡ软件仿真,FPGA器件验证实现。     

A 10 nm MOS and its applications

Microsystem Technologies - A 10 nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) are presented in this paper. A channel...     

一种低成本八位嵌入式MCU内核设计

本文介绍了一个低成本大的8位嵌入式微控制器内核设计，设计采用哈佛结构，双数据总线，指令系统兼容CYASM指令集。本文针对减小面积以实现低成本的目的，详细介绍了系统结构及各模块的设计思想和改进方法。     

基于单片机的8位频率计的设计

本文基于89C51单片机技术,介绍了一种数字式频率计数器,该频率计具有操作简单方便、响应速度快、体积小等一系列优点,可以及时准确地测量低频信号的频率。     

大容量NOR Flash与8位单片机的接口设计

在8位单片机系统中使用NOR Flash存储器,可以实现用简单设计完成复杂任务的目标,从而有效地缩短产品的开发周期,降低产品的制造成本.本文以NOR Flash存储器SST39SF040和MCS-51系列单片机为例,详细介绍大容量NOR Flash存储器与8位单片机的接口技术,给出硬件连接电路和扇区擦除操作的源程序代码.     

Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

Microsystem Technologies - This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS)...     

Parameter optimization of sub-35 nm contact-hole fabrication using particle swarm optimization approach

The major research focus on integrated circuits (ICs) mainly deals with increasing circuit performance and functional complexity of circuit. The lithography process is the most critical step in the fabrication of nanostructure for integrated circuit manufacturing. The most important variable in the lithography process is the line-width or critical dimensions (CDs), which perhaps is one of the most direct impact variables on the device performance and speed. This study presents a hybrid approach combining Taguchi’s robust design, back-propagation neural network modeling technique and particle swarm optimization (PSO) for sub-35 nm contact-hole fabrication in the lithography process. The BP neural network is employed to model the functional relationship between the input parameters and target responses. Particle swarm optimization is adopted to optimize the parameter settings through the well-trained BP model, where each particle is assessed using fitness function. The proposed PSO algorithm applies the velocity updating and position updating formulas to the population composed of many particles such that better particles are generated. Compared with realistic fabricated and measured data, this approach can achieve the optimal parameter settings for minimized CDs or target CDs. Meanwhile, it reduces the CD variation through the design of experiment. The experimental results show that the proposed approach dealing with the process modeling and parameter optimization demonstrates its feasibility and effectiveness for sub-35 nm contact-hole fabrication.     

一种嵌入于微处理器的8位乘加器的设计

给出了一种嵌入于微处理器,8bit×8bit+20bit并行MAC单元的设计;该设计可完成8bit整数或序数的乘法或乘加运算,具有整数乘加运算的饱和检测和饱和处理功能;设计中采用了一种新型Booth编码方法;对部分积压缩阵列进行了优化,将累加值作为一个部分积参与部分积压缩阵列的累加运算,节省了一级超前进位加法器;压缩阵列采用了一种新型4∶2压缩器,进一步缩短了延时,节省了面积。     

8位模型计算机自动测试系统的设计与实现

描述基于MCS-51的自动测试系统的设计,实现对8位模型计算机的自动测试过程。对8位模型计算机的测试流程进行详细分析,绘出模型机的存储器模块、运算器模块和控制器模块的测试流程图,编写各模块的C语言测试程序。通过大量实验。完成时8位模型计算机的自动测试,整机测试执行时间不超过10秒钟。     

Relationship between the attenuation of downwelling irradiance at 490 nm with the attenuation of PAR (400 nm-700 nm) in the Baltic Sea

The vertical attenuation coefficient of diffuse downwelling irradiance at 490 nm (K_d 490) is a parameter that we routinely derive from SeaWiFS images of the Baltic Sea. Here, through model simulations, we examine the relationship between K_d(490), and the vertical attenuation coefficient of PAR (K_d PAR), as this later coefficient determines the light available for aquatic photosynthesis. A simple semi-analytical model is used to predict K_d(490) and K_d(PAR), as a function of the concentrations of chlorophyll, colored dissolved organic material (CDOM), suspended inorganic, and suspended organic particulate material. A series of model simulations based on variations in these optically significant constituents over a range realistic for the Baltic Sea, are used to define the relationship between the two attenuation coefficients.

Kd(PAR)=0.6677Kd^0.6763(490).     

RF-MEMS for 5G applications: a reconfigurable 8-bit power attenuator working up to 110 GHz. Part 1: design concept,technology and working principles

RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy, is tested and discussed. In the current Part 1 of the contribution, the RF-MEMS power attenuator design concept is discussed. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises eight cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. In Part 2 of the article, fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in with a Finite Element Method software tool. Despite the attenuator complexity, the simulation approach leads to accurate prediction of the experimental behaviour. The device exhibits attenuation levels (S21) in the range from − 10 to − 60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3–5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. A comprehensive discussion is developed around the voltage standing wave ratio, employed as quality indicator for the attenuation levels. Finally, margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device.

     

8位单片机与以太网控制器RTL8029接口的VHDL设计

以CPLD为器件,采用VHDL语言,设计了51单片机与32位PCI总线以太网控制器RTL8029之间的接口逻辑,实现了8位单片机与32位以太网控制器之间的通信。     

声码器中一种四级可重构ALU的研究与设计

在面向语音编解码算法实现的高性能声码器设计中,支持可变长VLIW指令集的ALU单元是实现其设计目标的重要环节.本文提出一种四级可重构的ALU设计,以前缀算法加法器为核心,并通过操作数和资源的重构,能在单周期内完成81种复合算术逻辑运算,同时将其控制编码压缩了58.93%以适应指令集的宽度约束,高效实现了算法中潜在的高并行性,很好的满足了运算密集型的算法应用需求.