A reversible approach to two’s complement addition using a novel reversible TCG gate and its 4 dot 2 electron QCA architecture

Microsystem Technologies - Classical computers are already facing threshold limitations with CMOS getting restricted to clocking speeds in GHz range and alarming heat dissipation issues. Both these...     

Design and analysis of efficient QCA reversible adders

The Journal of Supercomputing - Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS...     

CMOS图象传感器发展状况

比较了CMOS图象传感器与CCD图象传感器的优缺点,分析了C MOS图象传感器的结构、研制现状、应用及市场前景。指出了随传感器技术的发展,CMOS图 象传感器可以代替CCD图象传感器,并预见了其发展趋势。     

CMOS有源图像传感器的最新研究进展

由于CMOS有源图像传感器在单片集成、系统功耗、价格以及微型化方面都大大优于CCD,近年来得到较快进展,特别是其抗辐射的性能,使其在空间应用方面尤其具有优势.介绍了CMOS有源图像传感器的原理、性能和研究进展,重点介绍了在空间领域,特别是星敏感器中的研究进展和应用现状.     

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.     

基于新型D触发器的双模前置分频器

在锁相环频率合成器中,双模前置分频器是一个速度瓶颈。分析了双模前置分频器的工作原理,提出了提高其工作速度的方法,包括给出一种新型高速CMOS动态D触发器的设计以及同步分频器的改进。经Cadence Spectre仿真,在0．8umCMOS工艺,电源电压为5V的条件下,最高频率达到了2．0GHZ,其速度和集成度远远超过静态CMOS电路。     

一种采用CDS电路的高精度温度传感器

采用相关双采(CDS)电路,设计了一种新颖的高精度温度传感器,该温度传感器可用于CMOS集成电路的过温检测。传感器的温度感应部分仅采用9个MOS管,其输出的包含温度信息的电流信号通过一个电容进行积分,随后采用CDS电路对积分信号进行消除kTC噪声和降低1/f噪声处理,并同时进行采样处理,得到与温度成正比的电压信号。该新型温度传感器与标准CMOS工艺兼容,且仿真结果表明其具有较高的性能。     

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits

An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed.this paper discusses its application in the design of multivalued circuits.Several current-mode CMOS quaternary and quinary circuits are designed by algebraic means.The design method based on this algebra may offer a design simpler than the previously known ones.     

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits

1IntroductionIntraditionalPostalgebra,amultivaluedfUnctionisexpressedbyusingMIN,MAXandLiteraloperations.SincetheMAXoperationhasmuchmorecomplicatedrea.lizationthansumoperationincurrellt-modeCMOSmultivaluedcircuit8,thePostalgebracannotefficielitlyguidethedesignofcurrent-modeCMOSmultivaluedcircuits.Inthepastfewy6arsanumberofcurrent-modeCMoSmultivaluedcircuitshavebeenpresented[1'2]andseveraldesignmethodshavebeenproposed-Amongthemthedesignmathodsbasedonacost-tableapproachandongraPhicdecom…     

CMOS technology trends and economics

CMOS has become the mainstream IC technology. Extending well into the sub-0.1-μm regime, its potential provides enormous chip complexities for integration of complete systems on one chip. A number of general trends in the development and manufacturing of CMOS technologies and ICs are discussed. It is argued that unrestricted availability of this technology is of strategic importance for the European high-technology industry. Exploding development costs and investments per technology generation require global cooperation, particularly for the relatively small European IC manufacturers to survive in this key technology. Trends in the development of 64-Mb and 256-Mb DRAMs, optical lithography processes, multilayer resist technologies, retrograde-well structures for CMOS device isolation, low-resistive and dense interconnection systems with low capacitances and silicon-on-insulator technology for the development of CMOS devices are described     

适用于低流速的恒温式液体流量传感器

给出一种能在低流速范围有较高灵敏度的液体流量传感器。在测量水的情形下,当流速为1cm/s时传感器的输出可达30mV,该灵敏度比类似条件下氮气敏感的灵敏度高约一个数量级。该传感器利用维持芯片温度恒定所需的加热功率的变化作为流速的量度。它由标准的铝栅CMOS工艺制成。     

GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45 nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.     

用于高速CMOS图像传感器的电容复用型循环ADC

设计了一种用于高速CMOS图像传感器的列并行标志冗余位(RSD)循环式模/数转换器(ADC)。该ADC在每次循环中采样和量化输入信号同步进行,速度比传统的循环式ADC提高了1倍。利用电容复用技术,对于像素输出信号的相关双采样(CDS)操作和精确乘2运算,将仅使用1个运放和4组电容来实现,减小了芯片面积。通过0.18μm标准CMOS工艺完成了ADC电路设计和仿真。SPICE仿真结果表明,在4 MS/s的采样速度和1.8 V电源电压下,ADC的SNDR达到55.61 dB,有效位数为8.94 bit,功耗为1.34 mW,满足10 bit精度高速CMOS图像传感器系统的应用要求。     

Thermal characterization of surface-micromachined silicon nitridemembranes for thermal infrared detectors

The aim of this work is to provide a thorough thermal characterization of membrane structures intended for thermal infrared detector arrays. The fabrication has been conducted at temperatures below 400°C to allow future post processing onto existing CMOS readout circuitry. Our choices of membrane material and processing technique were plasma enhanced chemical vapor deposited silicon nitride (SiN) and surface micromachining, respectively. The characterization gave for the thermal conductance (G) and thermal mass between the membrane and its surroundings 1.8·10^-7 W/K and 1.7·10^-9 J/K, respectively, which are close to the best reported values elsewhere. From these results the thermal conductivity and specific heat of SiN were extracted as 4.5±0.7 W/m.K and 1500±230 J/kg.K. The contribution to G from different heat transfer mechanisms are estimated. A model describing the pressure dependence of G was developed and verified experimentally in the pressure interval [5·10^-3, 1000] mbar. Finally, the influence of the thermal properties of the membrane on infrared detector performance is discussed     

CMOS电路电流测试综述

集成电路设计与测试是当今计算机技术研究的主要问题之一。ＣＭＯＳ电路的静态电流（ＩＤＤＱ）测试方法自８０年代提出以来,已被工业界采用,作为高可靠芯片的测试手段。近年来,动态电流（ＩＤＤＴ）测试方法正在研究中。现在正面临一些亟待解决的问题,希望闫家的参与。文中对ＣＭＯＳ电路电流测试方法作一综述。     

1.9GHz低电压低功耗CMOS射频低噪声放大器的设计

针对1.9GHzPHS和DECT无线接入系统的应用,提出了一种可工作于0.9V低电压的CMOS射频低噪声放大器,并对其电路结构、噪声及线性度等主要性能进行分析。该电路基于传统的折叠结构低噪声放大器,利用晶体管线性补偿技术,实现了低压低功耗下的高线性度。采用TSMC 0.18μm CMOS工艺模型设计与验证。     

Design, fabrication, and characterization of a submicroelectromechanical resonator with monolithically integrated CMOS readout circuit

In this paper, we report on the main aspects of the design, fabrication, and performance of a microelectromechanical system constituted by a mechanical submicrometer scale resonator (cantilever) and the readout circuitry used for monitoring its oscillation through the detection of the capacitive current. The CMOS circuitry is monolithically integrated with the mechanical resonator by a technology that allows the combination of standard CMOS processes and novel nanofabrication methods. The integrated system constitutes an example of a submicroelectromechanical system to be used as a cantilever-based mass sensor with both a high sensitivity and a high spatial resolution (on the order of 10/sup -18/ g and 300 nm, respectively). Experimental results on the electrical characterization of the resonance curve of the cantilever through the integrated CMOS readout circuit are shown.     

2．4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CMOS负阻LC压控振荡器的相位噪声．介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0．35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3．3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc／Hz。该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路。     

A novel CMOS process compatible high performance parallel-stacked RF spiral inductor

In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications.     

CMOS图像传感技术及其在影像产品中的应用

随着超大规模集成技术的发展，CMOS图像传感器显示出强劲的发展趋势。CMOS图像传感器具有在单芯片内集成时序和控制电路、A／D转换、信号处理等功能。本文介绍了CMOS图像传感器的结构和工作原理，并与CCD图像传感器进行比较，综述了CMOS图像传感器的最新进展及其在影像产品中的应用。