Design and analysis of efficient QCA reversible adders

The Journal of Supercomputing - Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS...     

Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology

This paper focuses on a novel design of an adder/subtractor-based incrementer/decrementer using quantum-dot cellular automata (QCA) technology. QCA is a promising nanotechnology that offers new techniques of computation and data transmission. We use the multilayer crossover technique in the proposed designs to achieve low latency and area for the scalability feature. Moreover, new designs of QCA half and full adders are proposed to improve the operating speed of the incrementer/decrementer. The working of the proposed designs is analyzed via the QCA simulator tool, and the results are compared with previous studies in terms of cell count, area, and latency. According to the analysis, the presented designs perform well; for example, the proposed 4-bit incrementer design shows an improvement of 65 % in terms of area usage and 3.2 times lower latency compared to its existing counterpart.     

FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic

The current paper explores the capability and flexibility of field programmable gate-arrays (FPGAs) to implement variable-precision floating-point (VP) arithmetic. First, the VP exact dot product algorithm, which uses exact fixed-point operations to obtain an exact result, is presented. A VP multiplication and accumulation unit (VPMAC) on FPGA is then proposed. In the proposed design, the parallel multipliers generate the partial products of mantissa multiplication in parallel, which is the most time-consuming part in the VP multiplication and accumulation operation. This method fully utilizes DSP performance on FPGAs to enhance the performance of the VPMAC unit. Several other schemes, such as two-level RAM bank, carry-save accumulation, and partial summation, are used to achieve high frequency and pipeline throughput in the product accumulation stage. The typical algorithms in Basic Linear Algorithm Subprograms (i.e., vector dot product, general matrix vector product, and general matrix multiply product), LU decomposition, and Modified Gram–Schmidt QR decomposition, are used to evaluate the performance of the VPMAC unit. Two schemes, called the VPMAC coprocessor and matrix accelerator, are presented to implement these applications. Finally, prototypes of the VPMAC unit and the matrix accelerator based on the VPMAC unit are created on a Xilinx XC6VLX760 FPGA chip. Compared with a parallel software implementation based on OpenMP running on an Intel Xeon Quad-core E5620 CPU, the VPMAC coprocessor, equipped with one VPMAC unit, achieves a maximum acceleration factor of 18X. Moreover, the matrix accelerator, which mainly consists of a linear array of eight processing elements, achieves 12X–65X better performance.     

Design and implementation of efficient QCA full-adders using fault-tolerant majority gates

The Journal of Supercomputing - CMOS technology is facing physical limitations in scaling the manufacturing process. Therefore, to deepen the development of better designs in a smaller area, it is...     

Characteristics of microring circuit using plasmonic island driven electron mobility

Microsystem Technologies - The plasmonic electronic component consists of the stacked layers of silicon–graphene–gold materials can be integrated with the driven group velocity system,...     

一种模拟量输出接口的设计

介绍了D／A转换芯片DAC7625和电压／电流转换芯片XTR110的原理及应用，采用DAC7625和XTR110，设计了一种DSP系统的模拟量输出接口。     

跨阻放大器自动静噪电路的设计与实现

采用0.35μm CMOS工艺设计并实现了一种新的应用于光纤通信跨阻放大器的自动静噪电路。提出的系统结构包括信号强度检测模块、比较基准产生电路、迟滞比较器和静噪控制单元。当输入信号减小到低于静噪使能阈值时,静噪模块将产生静噪使能信号,关闭信号通路;而当输入信号增大到高于静噪解除阈值时,静噪模块将产生静噪解除信号,打开信号通路。仿真结果表明,对于误码率10-10、灵敏度-40 dBm(100 nA)的155 Mb/s跨阻放大器,静噪使能和静噪解除两个阈值分别为47 nA和85 nA,静噪迟滞宽度为2.57 dB,满足系统要求。     

一种改进的M-BUS主机接口电路的设计与仿真

M-BUS(仪表总线)以远程供电及自由拓扑等特点被广泛应用于仪表或者传感器的通信中,而其带负载能力和接收处理能力是限制其应用范围的两个关键因素,为此,对现有的一种高驱动主机发送电路和传统的主机接收电路分别进行改进。发送电路通过调整电路结构,增加MOS管驱动电路和栅极保护电路,完善电路的关闭功能,从而在保持高驱动的同时,提高了电路运行的可靠性;接收电路采用差动运放对接收信号进行预处理再比较,提高了电路对变化负载的适应性和抗干扰能力。对改进后的发送电路和接收电路分别进行对比仿真,结果显示其收发性能均得到改善。     

实现线性传输的非线性光耦隔离电路的设计与分析

针对采用光敏二极管进行光耦合的线性光耦所搭建电路线性输出范围较窄的问题,选用光敏三极管进行光耦合的非线性双路光耦设计电路,并对电路进行了直流分析和低频交流分析。实验证明,该电路扩展了线性输出范围,并能有效地完成信号的采集任务。     

工业CO2激光器功率控制电路设计

在工业CO2激光器中,开关电源功率控制大多采用脉宽调制(PWM)方式.针对PWM调制方式,本文给出了基于芯片TDA4718的控制系统设计电路,它能产生频率及占空比可调的脉冲信号,该信号作用于开关器件,控制激光器输出功率的大小.     

基于LMP91000的电化学传感器调理电路设计

介绍了TI公司推出的新型电化学模拟前端芯片LMP91000,基于该芯片设计了新式化学传感器前端调理电路,并对电路进行了验证。采用该芯片可以大大简化电路设计,减少电路的复杂性,提高电路的可靠性。同时可编程的增益控制和温度补偿,能够实现电化学传感器的自动调零和智能校准,大大提高测量精度。芯片具有的I2C总线,可以实现传感器的阵列设计,实现多气体测量。     

漏电保护器的抗干扰性能研究与专用芯片实现

具体分析电网上的一种常见干扰信号——雷电干扰信号及RCCB现行国标在相关方面的不足;提出并引入了一项特殊技术——10 ms不驱动时间,以避开电网上特殊信号的干扰,减少误动作。将这项带延时保护功能的抗干扰技术与其他抗干扰技术集成进一块具有完全自主知识产权的漏电保护专用芯片中。实测结果证实,此芯片具有进口芯片及其国产仿制芯片所不具有的优良抗干扰能力。     

Ku波段星载行波管混合型预失真线性化器的研究

提出了一种改善行波管放大器非线性特性的预失真新方法,采用载波复幂级数法分析了星载行波管的非线性传输特性,提出一种反向复幂级数的预失真线性技术。所提出的预失真器非线性特性由混合型结构实现,包括肖特基二级管、砷化镓场效应管,改善了行波管在Ku波段的幅度-幅度失真特性,线性增益最大增加30dB,对行波管线性化器的后续研究有一定参考和实用价值。     

带有新型偏置电路的X波段低噪声放大器设计

针对温度等因素会改变三极管的静态工作点进而影响放大器性能的问题,采用一种直流偏置反馈控制技术,设计了一个X波段的低噪声放大器。同时,采用等资用功率增益圆和等噪声系数圆相结合的方法,以加快LNA的设计过程。对成品的实际测试和调试表明,此放大器达到了预定的技术要求,性能良好,其工作频率范围为10.2 GHz～10.8 GHz,噪声系数小于2 dB,增益达到34.5 dB,S参数S11优于-10 dB。     

Design of an electron beam stabilisation controller for a synchrotron

Synchrotrons are used to generate light for academic and industry research by accelerating electrons travelling in a circular path to relativistic speeds. In order to achieve optimum performance, electron beam stability is a crucial parameter for synchrotrons. This paper describes the design of a beam stabilisation controller, using Internal Model Control. Basis functions are used to identify the controllable components of the system and it is demonstrated how by selecting dynamics for each spatial mode, enhanced performance is achieved. The robust stability of the controller in the presence of spatial uncertainties is developed within an Integral Quadratic Constraint framework using two methods of spatial decomposition: Singular Value decomposition and Fourier decomposition. The controller has been implemented at Diamond Light Source, the UK׳s national synchrotron science facility. Results from the controller implementation are presented and it is demonstrated how the controller design and robust stability analysis are used to tradeoff performance and robustness.     

一种用于固态功率放大器的ALC电路

设计了一种用于X波段固态功放的ALC电路,根据输出信号功率控制可变衰减器的衰减量,对放大器的增益和输出功率进行调节。放大器工作频率范围为8.0 GHz～8.5 GHz。在室温条件下,当输入功率在-5 dBm～+5 dBm范围变化时,在ALC电路控制下放大器输出功率稳定在13.2 dBm～13.7 dBm之间,增益波动小于0.5 dB。     

Optimization of printed circuit board component placement using an efficient hybrid genetic algorithm

The hardware restrictions of surface mount placement machines, such as height, pick and place restrictions, and simultaneous pickup are often in printed circuit board (PCB)-related studies. This study proposes an efficient hybrid genetic algorithm (HGA) for solving the nozzle assignment problem and the component pick and place sequence problem. First, the proposed method obtains the sequence of the automatic nozzle changer (ANC) with the maximum number of simultaneous pickups and the minimum number of picks as the solution of the nozzle setup problem. Then, the proposed method uses the nearest neighbor search (NNS), 2-optimization, and a genetic algorithm (GA) with the known ANC sequences to obtain the PCB assembly time with the optimal component pick and place sequence. Experiments are conducted on the PCB of the EVEST EM-780 surface mount placement machine. Results show that the proposed HGA gives the lowest total number of picks, the shortest total head movement distance, and the minimum total PCB assembly time compared to those of other methods.     

Automated tuning of an electronic circuit board using the artificial neural network approach

Manufacturing of electronic circuits for microwave communication boards often requires tuning of different circuit characteristics by manual adjustment of several trimmer components, including the trimmer's resistance and capacitance. This manual tuning process was automated by applying the artificial neural network modeling approach. In the considered tuning process, which required manual adjustment of a set of trimmers, multiple specification criteria had to be satisfied by several trimmer rotations. The tuning process was described in terms of three independent steps: the circuit output measurement, trimmer selection, and trimmer rotation. The trimmer selection was performed by a semi-supervised neural network, which learned the patterns of circuit characteristics and the deviations between the ideal and practical outputs. Another network was developed for determination of trimmer rotation rate. The results, based on computer simulation of the tuning process, showed that the developed system improved performance of the tuning process, allowing for automation of the microwave circuit board tuning task in a real manufacturing environment.     

0.001 3 mm2自动频率校正算法电路的设计及应用

在高速串行接口PCIE2.0的设计中,为了保证数据传输的正确性,数据串行传输的工作时钟需要在很短的时间内完成锁定。为了减小锁相环的锁定时间,提高时钟稳定性,在传统的顺序搜索自动频率校正算法电路的基础上,提出了一种新的二进制搜索算法校正电路,并且应用于5 GHz的锁相环中,最大校正时间为22.5 μs。锁相环在SMIC 55 nm CMOS工艺下流片,SS工艺角下,AFC电路的面积为0.001 3 mm2。经测试,锁相环能够快速锁定,性能良好。