1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.     

Through-the-gate-implanted ultrathin gate oxide MOSFET's withcorner parasitics-free shallow-trench-isolation

We have realized direct-tunneling (DT) gate oxide (1.6 nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a corner parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel-doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench corner parasitics are eliminated by the advanced process architecture without increasing process complexity. Fully functional direct-tunneling oxide MOSFET's with excellent electrical characteristics confirm the feasibility of this novel approach     

High-quality deposited gate oxide MOSFET's and the importance ofsurface preparation

The fabrication and electrical characteristics of MOSFETs incorporating thin gate oxides deposited by a modified plasma-enhanced chemical-vapor-deposition (PECVD) process are reported. The gate oxide deposition and all subsequent steps were carried out at or below 400°C. These results represent the first demonstration of near-thermal-gate oxide quality. MOSFETs fabricated using a low-temperature PECVD gate oxide process without requiring a high-temperature anneal. The ultimate performance of the deposited oxide devices is shown to be critically dependent on the degree of process induced microroughness of the starting silicon surface. Low-temperature effective mobility measurements are used to compare inversion-layer scattering mechanisms in these devices     

Application of direct-tunneling gate oxides to high-performance CMOS

The characteristics of direct-tunneling gate oxide metal-oxide semiconductor field effect transistor (MOSFET)s are described. The effect of gate leakage current on MOSFET characteristics drops off as the gate length is reduced. Extremely good DC and AC performance has been realized using ultra-thin oxides down to 1.5 nm. Improved hot-carrier reliability and high oxide breakdown voltage have also been observed.     

Thermal-oxide gate GaAs MOSFET's

The first thermal-oxide gate GaAs MOSFET of the deep-depletion mode is reported. The gate oxide, which has been grown by the new GaAs oxidation technique in the As2O3vapor, is so chemically stable that it can be subjected to the fabrication process. Measurement of some dc characteristics of the device fabricated has shown a strikingly suppressed hysteresis.     

Ultrathin oxide-nitride gate dielectric MOSFET's

The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents     

Excellent immunity of GIDL to hot-electron stress in reoxidizednitrided gate oxide MOSFET's

The authors present an investigation of the enhancement in gate-induced drain leakage (GIDL) caused by hot-electron stress in MOSFETs with control oxides, nitrided oxides, and reoxidized nitrided oxides as gate dielectrics. The contributions of interface state generation and electron trapping to GIDL enhancement in these MOSFETs were compared based on stress condition and stress time dependencies. Although no improvement resulted at large drain biases, under low drain voltage conditions, reoxidized nitrided oxides exhibited less GIDL enhancement under hot-electron stress than a nitrided oxide that was not reoxidized     

Direct lateral profiling of hot-carrier-induced oxide charge andinterface traps in thin gate MOSFET's

A simple charge pumping method has been developed to measure the localized hot-carrier damage in scaled thin-gate MOSFET's. Lateral distributions of both interface traps and oxide charge can be derived directly from experimental charge pumping results without numerical simulation. By the use of this method, we have studied the erase-induced hot-carrier damage in flash EPROM devices, including the lateral distributions of both oxide charge (trapped holes) and interface traps. We discovered the following: the damage is confined within the source diffusion region with a rather wide distribution; the erase-induced oxide charge density is orders of magnitude more than erase-induced interface traps; both the peak density and width of the damage depend strongly on the junction bias during the erase operation. These results should be very useful for the reliability modeling and future device design of flash EPROM's     

Modeling hot-electron gate current in Si MOSFET's using a coupleddrift-diffusion and Monte Carlo method

A coupled two-dimensional drift-diffusion and Monte Carlo analysis is developed to study the hot-electron-caused gate leakage current in Si n-MOSFETs. The electron energy distribution in a device is evaluated directly from a Monte Carlo model at low and intermediate electron energies. In the region of high electron energy, where the distribution function cannot be resolved by the Monte Carlo method due to limited computational resources, an extrapolation technique is adopted with an assumption of a Boltzmann tail distribution. An averaging method is employed to extract the effective electron temperature. Channel hot electron injection into a gate via quantum tunneling and thermionic emission is simulated, and electron scattering in the gate oxide is taken into account. The calculated values of gate current are in good agreement with experimental results. The simulation shows that the most serious hot electron injection occurs about 200-300 Å behind the peak of average electron energy due to a delayed heating effect     

Charging effect of Si nanocrystals in gate oxide near gate on MOS capacitance

MOS structure with Si nanocrystals embedded in the gate oxide close to the gate has a much larger capacitance compared to a similar MOS structure without the nanocrystals. However, charge trapping in the nanocrystals reduces the capacitance dramatically, and after most of the nanocrystals are charged up the capacitance is much smaller than that of the MOS structure without nanocrystals. An equivalent-capacitance model is proposed to explain the phenomena observed.     

Submicron gate MOSFET's with channel-doped separate gate structures (SG-MOSFET's)

Submicron gate MOSFET's with a new device structure are presented. The device features gate separation between the source and gate and between the gate and drain. The minimum gate length limited by VTHlowering is extended into the submicron range. Experimental results showed pentode-like current-voltage characteristics without punchthtough, even in the submicron range. Experimental results of inverter circuits and theoretical analysis predict high-speed operation in the subnanosecond region.     

Gate-field-induced carrier heating in Si MOSFET's

We have used Si MOSFET's to study the variation of the channel Hall mobility and noise temperature with the gate voltage. From the Hall mobility measurements, a new empirical expression is found to describe the mobility degradation with gate voltage over a wide range of transverse electric field. By measuring the thermal noise, it is found that the channel carriers appear to be heated by the gate electric field and that the excess noise temperature varies quadratically with gate field.     

MOSFET's on Au-diffused high-resistivity Si substrates

Si MOSFET's on Au-diffused high-resistivity substrates were fabricated and their electrical properties were investigated. At 80 K, the current leakage between the source and drain of both n- and p-channel devices decreased below 10^-10A, and the devices exhibited normally-off behaviors. Au concentrations (N) in Si substrates as a function of diffusion temperature Tdiffwas determined from the change in the threshold voltage.Nversus Tdiffthus obtained is in fairly good agreement with that obtained by other methods. Dependence of effective mobility on Tdiffwas investigated in the form of a MOS device. The effective mobility decreased with increasing Tdiff, and it became clear that the diffusion temperature must be lower than about 700°C to obtain semi-insulating substrates with reasonably high carrier mobility. A C-MOS inverter was fabricated using an Au-diffused Si substrate, where no isolation wells were needed, in operation at low temperatures.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

Ultrathin gate oxide CMOS on (111) surface-oriented Si substrate

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a (111) surface-oriented Si substrate were investigated and compared with those on a (100) substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the (111) substrate is smaller than that on the (100) substrate and that of p-MOSFETs on (111) is larger than that on (100) until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for (100) and (111) substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the (111) substrate is slightly better than that on the (100) substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4° from (100) axis were investigated. It was found that there are few differences in the mobility between (100) and (100) 4° off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal (100) substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs     

Mo2N/Mo gate MOSFET's

Molybdenum nitride coatings on molybdenum, from a direct reaction of molybdenum with ammonia, are used to improve the gate electrode properties of Mo gate self-aligned MOSFET's. A Mo2N double-layer gate shows resistance against oxidation and processing reagents, and improved ion-implantation masking. The work function of the double-layer film was determined to be 4.69 ± 0.03 eV, which is independent of the nitride thickness and annealing conditions. The projected range of boron implantation is smaller in Mo2N than in Mo. A Mo2N coating of 870 Å over 2130- Å Mo masks up to 60-keV¹¹B and 120-keV⁷⁵As. The implantation study covers the energy range from 15 to 70 keV for boron and from 40 to 160 keV for arsenic.     

Physically-based threshold voltage determination for MOSFET's ofall gate lengths

A reliable method to determine the threshold voltage V_th for MOSFETs with gate length down to the sub-0.1 μm region is proposed. The method determines V_th by linear extrapolation of the transconductance g_m to zero and is therefore named “GMLE method”. To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined V_th values always meet the threshold condition, i.e., the onset of inversion layer buildup     

Width dependence of substrate and gate currents in MOSFET's

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.     

Miniaturization of Si MOSFET's at 77 K

Micrometer and submicrometer dimension Si MOSFET's have been studied at liquid nitrogen temperature. The emphasis of the study has been on the changes in the minimum channel length required for long-channel behavior Lmindue to cooling. It is found that there is a reduction in Lminwhich is quite considerable in MOSFET's with low-channel doping. We have shown that this effect is due to a shorter lateral depletion width, and therefore longer effective channel length at low temperatures. A drastic decrease in punchthrough current has also been observed.