Flow synchronization protocol

Presents an adaptive flow synchronization protocol that permits synchronized delivery of data to and from geographically distributed sites. Applications include inter-stream synchronization, synchronized delivery of information in a multisite conference, and synchronization for concurrency control in distributed computations. The contributions of this protocol in the area of flow synchronization are the ability to synchronize over arbitrary topologies, the introduction of an adaptive synchronization delay, the flexibility to maintain multiple synchronization groups, and the use of a modular architecture that permits the application to tailor synchronization calculations to its service requirements. The authors take advantage of network protocols capable of maintaining network clock synchronization in the millisecond range     

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding

Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.      

A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS

Modular arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular arithmetic more efficient is to identify algorithmic modifications that would enhance the parallelization of the target arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for algorithms based on modular arithmetic with several data dependencies. However, the mapping of generic algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of algorithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular arithmetic algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular arithmetic algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.     

椭圆曲线密码处理器的高效并行处理架构研究与设计

为了解决当前椭圆曲线密码处理器普遍存在灵活性低、资源占用大的问题,该文采用统计建模的方式,以面积-时间(AT)综合性能指标为指导,提出了一种面向椭圆曲线密码并行处理架构的量化评估方式,并确定3路异构并行处理架构可使处理器综合性能达到最优。其次,该文提出一个分离分级式存储结构和一个运算资源高度复用的模运算单元,可增强存储器的访问效率和运算资源的利用率。在90 nm CMOS工艺下综合,该文处理器的面积为1.62mm2,完成一次GF(2571)和GF(p521)上的点乘运算分别需要2.26 ms/612.4J和2.63 ms/665.4J。与同类设计相比,该文处理器不仅具有较高的灵活性、可伸缩性,而且其芯片面积和运算速度达到了很好的折中。     

Networked multimedia: the Medusa environment

The Medusa project at Olivetti Research aims to provide a networked multimedia environment in which many streams of multimedia data, perhaps thousands, are active simultaneously. Medusa uses a peer-to-peer architecture to control networked multimedia devices. In the software model presented to the applications programmer, active objects called modules represent cameras, displays, format converters, and so on. Data flows from module to module through connections between them, with proxy modules to restrict access for security reasons. The Medusa project is based on hardware that is a collection of asynchronous transfer mode (ATM) direct peripherals, including cameras, audio systems, multimedia storage servers, LCD displays, and televisions, as well as ATM networked workstations     

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integratedmedia chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm² /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule     

An architecture for real-time multimedia communication systems

A multimedia communication system includes both the communication protocols used to transport the real-time data and the distributed computing system (DCS) within which any applications using the protocols must execute. The architecture presented attempts to integrate these communications protocols with the DCS in a smooth fashion in order to ease the writing of multimedia applications. Two issues are identified as being essential to the success of this integration: the synchronization of related real-time data streams, and the management of heterogeneous multimedia hardware. The synchronization problem is tackled by defining explicit synchronization properties at the presentation level and by providing control and synchronization operations within the DCS which operate in terms of these properties. The heterogeneity problems are addressed by separating the data transport semantics (protocols themselves) from the control semantics (protocol interfaces)     

An architecture for a wavelength-interchanging cross-connectutilizing parametric wavelength converters

This paper proposes an architecture for a wavelength-interchanging cross-connect (WIXC) that can be used as a switching node of strictly transparent and scalable networks with all-optical routing and all-optical wavelength conversion capabilities. This architecture utilizes all-optical parametric wavelength converters based on difference-frequency-generation (DFG) or four-wave mixing (FWM), although this work focuses only on the implementation using difference-frequency-generation wavelength converters. The proposed WIXC architecture exploits the unique wavelength mapping properties of parametric wavelength converters: mirror image mapping and simultaneous multichannel wavelength conversion. The derivation of this architecture involves application of a space/wavelength transformation to the classical Benes switch fabric. The connection setup for the resulting architecture follows the well established looping algorithm, and the architecture is scalable in both the ports and the wavelengths. The scaling occurs in an orderly fashion, which allows modular upgrades of WIXC's for cost-effective evolution of the networks. The unique properties of the parametric wavelength converter including transparent and multichannel conversion capabilities result in a WIXC architecture that requires fewer wavelength converters while maintaining scalability and transparency     

Development of modular electrical systems

Modular systems provide the ability to achieve product variety through the combination and standardization of components. A methodology that combines system modeling, integration analysis, and optimization techniques for development of modular systems is presented. The approach optimizes integration and interactions of system elements and creates functional and physical modules for the electrical system. The Hatley/Pirbhai methodology (1987) is used for modeling functional requirements of a system. The model defines system interfaces (interactions) to support its functions. Once the interactions among functions are identified, an incidence matrix of the interfaces is developed. A clustering algorithm is developed to identify clusters in the incidence matrix, group the functions, and create modules. A Hatley/Pirbhai architecture model is developed to represent modular system design. A detailed discussion on the importance of system modeling in design of modular systems and on the constraints that limit development of modular vehicle systems is also presented. The approach presented is systematic and can be used to support product development and decision-making in engineering design     

Multichannel medium access control for ad hoc wireless networks

In this paper, we study the multichannel exposed terminal problem in multihop wireless networks. We propose a multichannel medium access control (MAC) protocol, called multichannel MAC protocol with hopping reservation (MMAC‐HR), to resolve the multichannel exposed terminal problem. MMAC‐HR uses two radio interfaces; one interface is fixed over the control channel, and the other interface switches dynamically between data channels. The fixed interface supports broadcast information and reserves a data channel for any data transmission. The switchable interface, on other hand, is for data exchanges and follows independent slow hopping without requiring clock synchronization. In addition, the proposed protocol is a distributed one. By using the ns‐2 simulator, extensive simulations are performed to demonstrate that MMAC‐HR can enhance the network throughput and delay compared with existing multichannel MAC protocol. Copyright © 2011 John Wiley & Sons, Ltd.     

基于IEEE1588精确时间同步的无线传感器网

无线传感器网(WSN)正在从要求不高的应用向要求更高的应用演进。分布式实体和事件的协调需要时间同步。虽然,已开发了很多用于WSN的时间同步方法,但某些应用需要高精度时间同步。精确时间同步支持应用的各种扩展。IEEE 1588精确时间协议(PTP)提供在一个网络中,一种具亚微秒精度、标准的设备同步方法。本文研究了在无线传感器网上,使用IEEE 1588的精确时间同步。使用IEEE 1588的精确时间同步提供了WSN中异构系统间的兼容性。     

雷达组网应用的体系结构研究

提出了一种基于以太网的雷达体系架构,该架构具有强大的扩展能力,能够适应各种应用环境,满足不同的组网需求。通过雷达处理单元(RPU)和交换机组合的转接,利用网络灵活的数据共享机制,将雷达天线与终端解耦和,使天线和终端都能够任意进行扩展。同时,对软件模块进行了改造和升级,使雷达能够接入广域网进行信息融合、互联互通,大大提升了雷达系统的探测能力和探测范围。     

Design and performance evaluation of active bandwidth brokers

With the arrivals of critical data transactions and multimedia applications, the needs of network services with different Quality of Service (QoS) guarantees increase rapidly. In order to ensure the delivery of information with a desired quality at the application layer, policy-based management (pbm) systems should be deployed at network service providers for configuring network devices properly. A policy-based management system is capable of resolving and enforcing policy rules in realizing end-to-end QoS for all kinds of network connections. In this paper, a novel design of policy-based management system based on active networks is proposed. Active network technology empowers network routers the ability to execute and move data and program code as needed. It is used in the proposed design (Active Bandwidth Broker architecture) to achieve the goals of system scalability and reliability. Moreover, policy control operations can be distributed among different active nodes. Thus, the architecture reduces the aggregate amount of policy control traffic in networks and expedites the response times on policy requests. Furthermore, the Policy Decision Point is a mobile agent that moves and avoids encountering network congestion situations. A system prototype has been constructed to implement the designed architecture. It has successfully demonstrated that the new design framework offers architecture flexibility, improves system reliability, and provides system scalability in handling a large number of service requests.     

Closer to the edge

The next generation of distributed systems will be loosely-coupled systems that: support incremental and independent development, and are tolerant of interface changes; can systematically deal with impedance mismatches; and work well in dynamically changing realtime situations; and can scale in complexity while delivering the required real-time performance. Popular architectural styles, including data flow architecture, event driven architecture and service-oriented architecture, can be regarded as special cases, by the appropriate assignment of roles and choice of quality of service in the interfaces between components. Data-oriented application architecture coupled with an appropriate standards based messaging software bus such as DDS can cut down the complexity of the integration problem from O(N*N) to O(N), while preserving loose-coupling and ensuring scalability. Having readily available middleware infrastructure bridges for popular application platform components can greatly boost productivity and the pace of integration     

模块化数据中心机房的实现方式

本文针对数据中心机房提出模块化设计理念,可以有效解决现有数据中心的一些问题,使数据中心具备灵活性、可扩展性、高标准、绿色节能、并能降低人力成本。本文重点介绍了模块化数据中心的实现方式。     

Future test systems architectures

The expanding number of test system architectural choices has caused confusion in the test engineering community. In this article, we explore the strengths and weaknesses of the existing test system architectures, including rack and stack systems with general-purpose interface bus (GPIB) instruments and modular systems. We provide a glimpse into an emerging new architecture: LAN-based test systems. The article reviews key concerns such as costs, channel counts, footprints, I/O speeds, ease-of-integration, and flexibility. The objective of the article is to provide engineers insight into the most effective test systems for their future applications.     

高性能可扩展公钥密码协处理器研究与设计

 本文提出了一种高效的点乘调度策略和改进的双域高基Montgomery模乘算法,在此基础上设计了一种新型高性能可扩展公钥密码协处理器体系结构,并采用0.18μm 1P6M标准CMOS工艺实现了该协处理器,以支持RSA和ECC等公钥密码算法的计算加速.该协处理器通过扩展片上高速存储器和使用以基数为处理字长的方法,具有良好的可扩展性和较强的灵活性,支持2048位以内任意大数模幂运算以及576位以内双域任意椭圆曲线标量乘法运算.芯片测试结果表明其具有很好的加速性能,完成一次1024位模幂运算仅需197μs、GF(p)域192位标量乘法运算仅需225μs、GF(2^m)域163位标量乘法运算仅需200.7μs.     

基于FPGA的多功能阵列信号处理系统设计

为了适应阵列信号处理数据量大、实时性高的特点,文中结合项目需求设计了一种基于FPGA的多功能阵列信号处理系统。通过采用先进的大规模高性能FPGA和多路高精度ADC芯片,可完成对40路中频信号的同步采集和数字下变频处理,并由数字波束合成运算得到36组波束数据。通过设置多种类型的对外接口,可实现与多个外联设备的网络数据交互、串口控制、波束控制及MGT高速数据传输。文中给出了系统的硬件和软件总体架构设计,并详细介绍了芯片选型、外设接口及各软件功能模块的具体实现方法。测试结果表明,本系统满足设计需求,具有较强的阵列信号处理能力以及良好的通用性和可扩展性。     

A modular massively parallel computing approach to image-relatedprocessing

A modular massively parallel computing (Modular-MPC) philosophy to image-related processing is discussed in this paper The approach is based on application-specific configurations of generic fine-grain Single Instruction stream operating on Multiple Data (SIMD) streams massively parallel computing modules to achieve high performance and maximal flexibility and programmability while remaining cost-effective. The need for a software architecture to allow programming such systems is highlighted and the implementations on current Modular-MPC systems are described. The experience with ASTRA, a Modular-MPC testbed system, in image related application development and system performance has led to a technology road-map using VLSI, MCM, and monolithic WSI technologies aiming at `future proofing' of the Modular-MPC concept and systems achieving T (10¹²) operations per second performance. This experience and progress are discussed together with the implementation of three image-related processing applications     

一种新的网络对象存储设备研究

Internet的飞速发展对于存储系统的可扩展性提出了很高的要求,也带来了由数据模型与存储模型的不一致问题引起的服务器性能瓶颈现象.针对这些情况,本文提出了网络对象附属存储设备(NAOSD)的概念,其利用设备处理器的能力直接支持结构化数据存储.这一设计减少了存储系统中数据服务器的负载,增加了系统吞吐量.同时,研究了该设备原型在集群环境中的应用,提出了数据/元数据统一存储与查询式数据定位机制.分析表明,这些机制能够较显著地提高系统扩展性——数据访问时间随系统规模的扩大呈对数增长,优于传统的映射定位机制.我们已经模拟实现了NAOSD,并在性能比较测试中取得了较好的效果.