A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply

We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm² chip consumes 8.5 mW from a 0.5 V supply.     

Design of a full-band CMOS UWB receiver and fast-hopping carrier generator for 3.1–10.6 GHz

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1–10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1–10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm² including the bond pads.     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A CDMA2000 zero-IF receiver with low-leakage integrated front-end

This paper describes a highly integrated CDMA 2000 US-CEL band (880-MHz) receiver. The single-chip zero-IF design incorporates all receiver signal-path functions including the low-noise amplifier (LNA) on a single die. The complete receiver design exceeds the stringent linearity and local oscillator (LO) leakage requirements for this standard arising from the coexistence with narrow-band FM signals. The integrated LNA achieves 1.0-dB noise figure with +9-dBm IIP3 at high gain, and by maintaining LO leakage to the antenna port well below -80 dBm at all gain settings, no external LNA is required. The receiver is fabricated in a 0.25-/spl mu/m 40-GHz f/sub t/ BICMOS technology, and occupies 3 mm/sup 2/.     

An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers

An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters

Low-distortion I/Q baseband filters interface with a 2.5 GHz RF receiver front-end configured as a Gm-cell in a direct-conversion architecture targeted towards WLAN 802.11b application. The active I/Q current-mode filters use AC current to carry the large swing of both desired and blocker signals, relaxing the voltage headroom requirement to a 1.2 V supply. An on chip master–slave automatic tuner is used to lock the filter bandwidth to a precision 20 MHz reference crystal oscillator, resulting in a $≪ ,$3% tuning accuracy and $≪, $ 0.5% I/Q bandwidth matching. The receiver achieves a 3.2 dB DSB NF, ${-}$14 dBm out-of-band IIP3, and ${+}$ 27 dBm worst case IIP2, all referred to the LNA input, while drawing 30mA from a 2.7 V supply. The chip is fabricated in a 0.5 $mu$m 46 GHz $f_{T}$ SiGe BiCMOS process. The active area is 2.54 mm$^{2}$ .