A 700-MHz switched-capacitor analog waveform sampling circuit

Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-μm CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single +5 V supply is 2 mW     

An 8-Gb/s capacitively coupled receiver with high common-mode rejection for uncoded data

An 8-Gb/s receiver is demonstrated in 0.35-/spl mu/m SiGe with two on-chip 60-fF ac-coupling capacitors. These capacitors are formed by on-chip metal layers and have a breakdown voltage of at least /spl plusmn/690 V, which is the dc input range of the receiver. The receiver especially resists strong ac common-mode edges with a slew rate up to 4V/ns for enhanced EMI rejection. The self-clocked quantized feedback technique used, features uncoded data that contains long sequences of consecutive identical digits or ac-unbalanced data. The differential input sensitivity is 0.5-1.1Vpp with a supply voltage between 2.5 and 3.5 V.     

An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm/sup 2/, out of a total unit area of 35 mm/sup 2/.     

A new design of power supplies for pocket computer systems

A new design of power supply based on the idea of switched capacitors, as applied to pocket computer systems, is presented. This new type of power supply is inductorless and, consequently, suitable for hybridization and even monolithic integration. The new design is also based on distinguishing characteristics of pocket digital computer systems, in which a switched-capacitor converter can work well, since minimal regulation is required. The new device may enable the pocket computer system to be powered by only one battery, resulting in a simple topology. Two switched-capacitor converters, +12 V/-12 V, +5 V and +5 V/+12 V, -12 V, are shown, respectively, as an example for demonstrating the basic principle and its performance. PSPICE simulation and laboratory models show good results for this new type of power supply     

A 2-μm BiCMOS process utilizing selective epitaxy

A 2-μm BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2-μm CMOS process with a poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors     

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm² was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 μV and 47 μV in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V     

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm² in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW     

A systematic realization of third-order quadrature oscillator with controllable amplitude

A systematic realization of third-order quadrature oscillator using a voltage-mode non-inverting lowpass filter and a voltage-mode inverting lossless feedback integrator is presented in this paper. The proposed circuit consists of two multiple-output differential voltage current conveyor transconductance amplifiers (MO-DVCCTAs), two grounded resistors and three grounded capacitors. The new circuit provides three quadrature voltage outputs, two high-impedance quadrature current outputs, and one high-impedance current output with controllable amplitude, simultaneously. When the input bias current of the first MO-DVCCTA is a modulating signal, the circuit can generate amplitude modulation or amplitude shift keying signals. The condition of oscillation and the frequency of oscillation can be controlled independently through grounded resistors. The proposed circuit only uses grounded capacitors and grounded resistors, which can be easily implemented as an integrated circuit. The experimental results and H-Spice simulation results are given to confirm the theoretical analysis.     

A Single-Inductor Switching DC–DC Converter With Five Outputs and Ordered Power-Distributive Control

An integrated five-output single-inductor multiple-output dc-dc converter with ordered power-distributive control (OPDC) in a 0.5 mum Bi-CMOS process is presented. The converter has four main positive boost outputs programmable from +5 V to +12 V and one dependent negative output ranged from -12 V to -5 V. A maximum efficiency of 80.8% is achieved at a total output power of 450 mW, with a switching frequency of 700 kHz. The performance of the converter as a commercial product is successfully verified with a new control method and proposed circuits, including a full-waveform inductor-current sensing circuit, a variation-free frequency generator, and an in-rush-current-free soft-start method. With simplicity, flexibility, and reliability, the design enables shorter time-to-market in future extensions with more outputs and different operation requirements.     

High density, low leakage Back-End 3D capacitors for mixed signals applications

ITRS 2018 compliant capacitors have been developed with low-cost anodic Ta₂O₅ material. High capacitance values and very low leakages have been obtained on low thermal budget capacitors fabricated with a CMOS-compatible process. High densities in the order of 10 fF/μm² and very low leakages down to 10⁻⁷ A/cm² at 10 V have been measured electrically. All these features, combined with a high breakdown voltage superior to 37 V and linearity coefficient down to 82 ppm/V, make such capacitors great candidates for both analog precision and decoupling applications.     

A novel program-erasable high-/spl kappa/ AlN-Si MIS capacitor

We demonstrate a programmable-erasable MIS capacitor with a single layer high-/spl kappa/ AlN dielectric on Si having a high capacitance density of /spl sim/5 fF//spl mu/m/sup 2/. It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al/sub 2/O/sub 3/, AlON, or other known high-/spl kappa/ dielectric capacitors, where the threshold voltage (V/sub th/) shifts continuously with voltage. This device exhibits good data retention with a V/sub th/ change of only 0.06 V after 10 000 s.     

A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC

A set of power minimization techniques is proposed for pipelined ADC's. These techniques include commutating feedback-capacitors, sharing of the op-amp between the adjacent stages of the pipeline, reusing the first stage of the op-amp as comparator pre-amp, and exploiting parasitic capacitors for common-mode feedback. This set of low-power design techniques is incorporated in an experimental chip fabricated in a 1.2-μm, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, the chip dissipates 33 mW of power from a 2.5-V analog supply while achieving a maximum differential nonlinearity (DNL) of -0.78 and +0.63 least-significant bits (LSB) with a peak signal-to-noise ratio (SNR) of 67.6 dB     

H2712Qb型多路电源模块的研制

成功研制了H2712Qb型DC/DC变换多路电源模块。通过对+5V和–12V电路的详细讨论,介绍了该产品的电路原理,并对元件选取、厚膜平面化、减小体积、降低纹波、提高可靠性和实现不平衡加载等问题提出了见解和相应的解决方法。该电源模块输出为+15V、+12V、–12V和+5V,功率为30W,预计可靠性达1.17×105h。     

非单调线性变化且可变位的双DAC电路设计

本文设计了一个数字输入和模拟输出呈斜锯齿波变化且位数可在７、１１、１５、１９位４种结果中选择的双ＤＡＣ电路。它设计在一单片机内，作掌型电脑的声音控制。     

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.     

A Double Sampling 8-Bit, 50 MS/s, 32 mW Pipeline Converter with +6 dB Overdrive Headroom

An 8-bit, 50 MS/s pipeline converter is presented with peak SNR and SFDR of 43.1 dB and 52.5 dB, corresponding to effective number of bits of 6.9. The circuit is implemented in a 0.35 m CMOS process, the core area is 0.36 mm² and its analog and digital current consumptions (including I/O buffers) are 6.2 mA and 4.5 mA from a 3 V supply. The low power consumption is achieved by using two banks of sampling capacitors (double sampling) and a mixed architecture giving 1+1+1+2+3 bits per stage. The mixed architecture means that a full ninth bit cannot be coded, but instead it is a employed as an almost 6 dB overdrive input range. The maximum allowable comparator errors in different architectures are calculated and the benefits of excess redundancy are discussed.     

A single chip FSK modem

In the development of a fully LSI-designed single-chip 300-b/s asynchronous FSK modem, two `hard to beat' problems are: (1) to build both analog and digital circuits on-chip in-such a way that the modem performance is practically free from line noise and transmission distortion; and (2) to meet the requirement (CCITT V.21) of a +5 dBm level margin to discriminate carrier-on from carrier-off under the rigid operating conditions expected. It was found that a combination of high-gain limiter, digital PLL, and postdetection filter in the demodulator section was useful to solve the first problem. A combination of a stabilized rectifier and voltage reference generator contributed to the solution of the second problem. Measurements on chips indicated at /spl plusmn/12% isochronous distortion in the received signal level range of -5 to -45 dBm, a 10/SUP -5/ bit error rate at an SNR of 3 dB, and /spl plusmn/0.15 dB carrier detection level deviation over the temperature range from -20 to +100/spl deg/C within the supply voltage variations of /spl plusmn/10%. Switched-capacitor filters were used throughout the analog section. The device requires two power supplies, +12 and +5 V. The power consumption is 85 mW, and the chip size is 5.9/spl times/5.4 mm.     

A ratio-independent algorithmic analog-to-digital conversion technique

An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.     

A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm² in a 1 μm CMOS process     

一种新颖的基于CCCⅡ的多功能滤波器

提出了一种采用新的电流控制传送器(CCCII)积木块构成的电流模式单输入、多输出的多功能滤波器电路,它仅由4个CC器件和2个电容构成,选择电路3个输出端中的1个或它们的组合,即可实现5种基本的二阶滤波功能,给出了电路的PSPICE仿真结果,验证了理论分析的正确性。