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1.
In this paper, a local weighted interpolation method for intra-field deinterlacing is proposed as an improved version of the DCS (deinterlacing with awareness of closeness and similarity) algorithm. The original DCS method is derived from bilateral filter which takes the local spatial closeness and pixel similarity into account when calculating the weight of interpolation. The proposed algorithm achieves three improvements: 1) instead of the line average, a more accurate interpolation filter is used to estimate the center missing pixel; 2) the center-independent interpolation method is proposed to replace the center-dependent interpolation strategy; 3) the adaptive weighted interpolation method is used to improve the accuracy of interpolation. Experimental results show that the proposed algorithm provides superior performance in terms of both objective and subjective image qualities when compared with other conventional benchmarks, including DCS algorithms with low complexity.  相似文献   

2.
图像插值是将低分辨率图像放大后提高视觉效果的有效方法,传统算法中有较简单且算法复杂度小的方法,但插值后的图像常常有锯齿边缘或者效果模糊,因而实际应用并不广泛。为克服以上缺陷,提出了一种先将图像进行区域划分,然后再进行快速图像插值的算法,既保证了算法较低的复杂度,又优化了图像显示效果,适合实际应用。  相似文献   

3.
薄板样条函数是空间插值中的一种重要方法。对于巨幅影像数据使用薄板样条函数进行空间插值时,可能会出现运行时间太长,以及计算机内存空间不足或程序运行无响应的问题。针对这些问题,根据薄板样条函数光滑、连续的特点,基于GDAL开源函数库,提出对巨幅影像数据的分块读取,在块内利用并行技术求解线性方程组,确定薄板样条函数,最后进行空间插值的方法。结果表明,该方法可以有效的解决这些问题。  相似文献   

4.
Scalable video coding (SVC) is a newly emerging standard to be finalized as an extension of H.264/AVC. The most attractive characters in SVC are the inter layer prediction techniques, such as Intra_BL mode. But in current SVC scheme, a uniform up-sampling filter (UUSF) is employed to magnify all components of an image, which will be very inefficient and result in a lot of redundant computational complexity. To overcome this, we propose an efficient component-adaptive up-sampling filter (CAUSF) for inter layer interpolation. In CAUSF, one character of human vision system is considered, and different up-sampling filters are assigned to different components. In particular, the six-tap FIR filter used in UUSF is kept and assigned for luminance component. But for chrominance components, a new four-tap FIR filter is used. Experimental results show that CAUSF maintains the performances of coded bit-rate and PSNR-Y without any noticeable loss, and provides significant reduction in computational complexity. Supported by China Postdoctoral Science Foundation (Grant No. 20080430454), the Key Laboratory of Geo-informatics of State Bureau of Surveying and Mapping (Grant No. 200834), the National High-Tech Research and Development Program of China (Grant No. 2007AA12Z151), and the National Basic Research Program of China (Grant No. 2006CB701303)  相似文献   

5.
为充分利用视频的时空联系去噪,提出了视频的刚体模型.刚体模型以线性关系组织视频的像素,结合了像素间的时域和空域关联,可以通过主色调区域划分和边缘句法匹配获得视频的刚体分解及其对应关系.基于刚体模型的插值去噪利用像素值的空域邻近性和时域稳定性联合判断插值像素的参考价值.对常用测试视频的去噪实验表明了刚体模型的正确性,基于刚体模型的插值去噪方法在视觉效果和峰值信噪比上都表现出色.  相似文献   

6.
智能视频监控技术在公共安全、交通管理、智慧城市等方面有着广泛的运用前景,需求日益增长。随着摄像头安装的数量越来越多,采集的图像数据量越来越大,靠单台计算机处理已经远远不能满足需求了。分布式计算的兴起与发展为解决大规模的数据处理问题提供了很好的途径。使用一种基于Spark Streaming的视频/图像流处理的测试平台,阐述了平台的构成和工作流程,深入研究各个参数对集群性能的影响,创新性地提出了CPU时间占用率作为性能评估指标,与总的处理时间结合,更为全面反映集群性能和资源利用率。  相似文献   

7.
To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.
Luca FanucciEmail:

Sergio Saponara   got the Laurea degree, cum laude, and the Ph.D. in Electronic Engineering from the University of Pisa in 1999 and 2003, respectively. In 2002, he was with IMEC, Leuven (B), as Marie Curie Research Fellow. Since 2001, he collaborates with Consorzio Pisa Ricerche-TEAM in Pisa. He is senior researcher at the University of Pisa in the field of VLSI circuits and systems for telecom, multimedia, space and automotive applications. He is co-author of more than 80 scientific publications. He holds the chair of electronic systems for automotive and automation at the Faculty of Engineering. Michele Casula   received the Laurea degree in Electronic Engineering from the University of Pisa in 2005. Since 2006, he is pursuing a Ph.D. degree in Information Engineering at the same university. His current interests involve VLSI circuits design, computer graphics, and Network-on-Chips. Luca Fanucci    received the Laurea degree and the Ph.D. degree in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with ESA/ESTEC, Noordwijk (NL), as a research fellow. From 1996 to 2004, he was a senior researcher of the Italian National Research Council in Pisa. He is Professor of Microelectronics at the University of Pisa. His research interests include design methodologies and hardware/software architectures for integrated circuits and systems. Prof. Fanucci has co-authored more than 100 scientific publications and he holds more than ten patents.  相似文献   

8.
针对传统的3种图像插值算法在插值后分别存在灰度不连续、轮廓模糊、计算量大等问题,提出了一种新的区域插值算法。该算法先对图像依据纹理平坦或复杂进行区域的相对划分,然后根据待插值点在源图像中所属的区域对应地使用不同的插值算法。与一些典型插值算法进行仿真比较,验证了该算法在基本不改变插值精度的前提下,可以有效地降低运算时间。  相似文献   

9.
High definition (HD) and ultra-high definition (UHD) digital TV require high-resolution images and lots of data transfers between processors and memory devices often become the bottleneck of the system. Video and image signal processing usually require blocks of square or rectangular shaped pixel data for signal processing. It requires frequent precharging and activating new rows, and results in extra latencies for reading and writing pixel data in memory devices. This paper proposes an efficient memory controller for video and image processing to reduce the latencies for reading and writing blocks of pixel data. The controller stores a frame of pixel data by distributing contiguous lines of pixel data to multiple banks in sequence. Its efficiency is enhanced more with an interface protocol such as AMBA AXI in which outstanding transactions are allowed. Memory controllers according to the proposed scheme are designed and the performance and the efficiency are compared with the previous works.  相似文献   

10.
一种鲁棒性的基于运动估计的自适应时空域视频去噪算法   总被引:4,自引:0,他引:4  
提出了一种鲁棒的基于运动估计的自适应时空域视频去噪算法。在运动估计前的自适应维纳滤波,提高了运动估计的准确性与匹配率;在运动估计后基于小块的再次判断以及Duncan滤波器的采用,提高了运动估计的鲁棒性。实验数据表明,此算法取得了很好的预期效果。  相似文献   

11.
针对传统彩色滤波阵列(Color Filter Array,CFA)插值算法在图像识别前一般需要对彩色图像预处理,其中包括把插值后的彩色图像转化为灰度图像、平滑内部和锐化边缘,过程较为繁琐的问题,提出一种新的基于图像增强的灰度插值算法,即在插值过程中锐化图像的边缘并平滑内部,插值结果直接是一幅灰度图像并且保证图像的几何特性不变.实验结果表明此算法的有效性.  相似文献   

12.
This article proposes a parameter extraction algorithm based on adaptive interpolation fitting. By adaptively inserting interpolation points within a given interval, the number of the sampling points in the extraction process can be greatly reduced, which makes the calculation more efficient. Furthermore, the effect of noise can be eliminated with the multipath characteristic of the algorithm. The specific algorithm flow is given in detail. And two microwave filter design examples verified the feasibility and effectiveness of the proposed algorithm.  相似文献   

13.
Silicon-based digital cameras can record visible and near-infrared (NIR) information, in which the full color visible image (RGB) must be restored from color filter array (CFA) interpolation. In this paper, we propose a unified framework for CFA interpolation and visible/NIR image combination. To obtain a high quality color image, the traditional color interpolation from raw CFA data is improved at each pixel, which is constrained by the corresponding monochromatic NIR image in gradient difference. The experiments indicate the effectiveness of this hybrid scheme to acquire joint color and NIR information in real-time, and show that this hybrid process can generate a better color image when compared to treating interpolation and fusion separately.  相似文献   

14.
基于Coons-Gordon造型原理,研究了插值两族相交截面线采样点的B样条曲面双向插值造型算法。参数化各采样点并计算每条截面线的节点矢量,估算每条截面线对应的曲面参数,根据每条截面线的节点分布以及另一族截面线对应的曲面参数统一节点矢量。分别插值两族截面线采样点及其公共点得到三张B样条曲面,其布尔和即为插值两族截面线采样点的B样条插值曲面。实例表明,得到的双向插值曲面控制顶点数少,光顺性好。  相似文献   

15.
Image interpolation is a very important branch in image processing. It is widely used in imaging world, for example, image interpolation is often used in 3-D medical image to compensate for information insufficiency during image reconstruction by simulating additional images between two-dimensional images. Reversible data hiding has become significant branch in information hiding field. Reversibility allows the original media to be completely restored without any degradation after the embedded messages have been extracted. This study proposes a high-capacity image hiding scheme by exploiting an interpolating method called Interpolation by Neighboring Pixels (INP) on Maximum Difference Values to improve the performance of data hiding scheme proposed by Jung and Yoo. The proposed scheme offers the benefits of high embedding capacity with low computational complexity and good image quality. The experimental results showed that the proposed scheme has good performance for payload up to 2.28 bpp. Moreover, the INP yields higher PSNRs than other interpolating methods such as NMI, NNI and BI.  相似文献   

16.
As we all know, video frame rate determines the quality of the video. The higher the frame rate, the smoother the movements in the picture, the clearer the information expressed, and the better the viewing experience for people. Video interpolation aims to increase the video frame rate by generating a new frame image using the relevant information between two consecutive frames, which is essential in the field of computer vision. The traditional motion compensation interpolation method will cause holes and overlaps in the reconstructed frame, and is easily affected by the quality of optical flow. Therefore, this paper proposes a video frame interpolation method via optical flow estimation with image inpainting. First, the optical flow between the input frames is estimated via combined local and global-total variation (CLG-TV) optical flow estimation model. Then, the intermediate frames are synthesized under the guidance of the optical flow. Finally, the nonlocal self-similarity between the video frames is used to solve the optimization problem, to fix the pixel loss area in the interpolated frame. Quantitative and qualitative experimental results show that this method can effectively improve the quality of optical flow estimation, generate realistic and smooth video frames, and effectively increase the video frame rate.  相似文献   

17.
This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image compression technique. The improvement is achieved by employing a Hopfield neural network (HNN) to calculate a cost function upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus resulting in better compression ratios. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The implementation exploits the inherent parallelism of the BTC/HNN algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113 × 106 of pixels per second with a compression ratio which varies between 1.25 and 2 bits/pixel, according to the image nature.  相似文献   

18.
胡顺波 《计算机应用》2011,31(8):2225-2228
针对B样条GPVE插值法和B样条滤波法产生归一化互信息(NMI)测度伪极值点的原因,结合它们导致联合直方图聚散程度的互补效果,提出了各阶B样条滤波和GPVE的融合插值算法。通过图像之间的刚体配准实验,从测度曲线光滑性能和极值点数目方面,对比分析了一阶、三阶、五阶B样条滤波法,B样条GPVE插值法和新提出的融合插值算法。实验结果表明,提出的各阶B样条融合插值算法的配准性能都优于对应阶次B样条滤波法和B样条GPVE插值法。  相似文献   

19.
An adaptive window mechanism for image smoothing   总被引:2,自引:0,他引:2  
Image smoothing using adaptive windows whose shapes, sizes, and orientations vary with image structure is described. Window size is increased with decreasing gradient magnitude, and window shape and orientation are adjusted in such a way as to smooth most in the direction of least gradient. Rather than performing smoothing isotropically, smoothing is performed in preferred orientations to preserve region boundaries while reducing random noise within regions. Also, instead of performing smoothing uniformly, smoothing is performed more in homogeneous areas than in detailed areas. The proposed adaptive window mechanism is tested in the context of median, mean, and Gaussian filtering, and experimental results are presented using synthetic and real images and compared with a state-of-the-art method.  相似文献   

20.
This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.
Giovanni RamponiEmail:

Sergio Saponara   is a Research Scientist and Assistant Professor at the University of Pisa. He was born in Bari, Italy, in 1975. He received the Electronic Engineering degree cum laude and the Ph.D. in Information Engineering, both from Pisa University, in 1999 and 2003, respectively. Since 2001 he collaborates with Consorzio Pisa Ricerche, Italy and in 2002 he was with IMEC, Belgium as Marie Curie research fellow. His research and teaching interests include electronic circuits and systems for multimedia, telecom and automation. He co-authored more than 40 papers including journals, conferences and patents. Luca Fanucci   is Associate Professor of Microelectronics at the University of Pisa. He was born in Montecatini, Italy, in 1965. He received the Doctor Engineer degree and the Ph.D. in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with the European Space Agency's Research and Technology Center, Noordwijk, The Netherlands, and from 1996 to 2004 he was a Research Scientist of the Italian National Research Council in Pisa. His research interests include design technologies for integrated circuits and systems, with emphasis on system-level design, hardware/software co-design and low-power. He co-authored more than 100 journal/conference papers and holds more than 10 patents. Stefano Marsi   was born in Trieste, Italy, in 1963. He received the Doctor Engineer degree in Electronic Engineering (summa cum laude) in 1990 and the Ph.D. degree in 1994. Since 1995 he has held the position of researcher in the Department of Electronics at the University of Trieste where he is the teacher of courses in electronic field. His research interests include non-linear operators for image and video processing and their realization through application specific electronics circuits. He is author or co-author of more than 40 papers in international journals, proceedings of international conferences or contributions in books. Giovanni Ramponi   is Professor of Electronics at the Department of Electronics of the University of Trieste, Italy. His research interests include nonlinear digital signal processing, and the enhancement and feature extraction in images and image sequences. Prof. Ramponi has been an Associate Editor of the IEEE Signal Processing Letters and of the IEEE Transactions on Image Processing; presently is an AE of the SPIE Journal of Electronic Imaging. He has participated in various EU and National Research Projects. He is the co-inventor of various pending international patents and has published more than 140 papers in international journals and conference proceedings, and as book chapters. Prof. Ramponi contributes to several undergraduate and graduate courses on digital signal processing.   相似文献   

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