A low-power integrated circuit for remote speech recognition

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 μW at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-μm, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 μJ. It achieves recognition rates over 98% in isolated-word speech recognition tasks     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2 V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33 ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100 MHz, the power consumption is 30 µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4 dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.     

A low-power circuit block for digital telephone exchanges

An integrated static 128 bit serial memory with logic circuitry at its input and transmission line drivers at its output is described. It works at a supply voltage of ?2 V ± 17%. Its power dissipation is 90 mW, and its maximum clock frequency is 40 MHz. Chip size is 3 × 4 mm².     

A high-performance, low-power complementary coupled BiCMOS circuit

Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

A low-power readout circuit for nanowire based hydrogen sensor

This paper presents a fully integrated lock-in amplifier intended for nanowire gas sensing. The nanowire will change its conductivity according to the concentration of an absorbing gas. To ensure an accurate nanowire impedance measurement, a lock-in technique is implemented to attenuate the low frequency noise and offset by synchronous demodulation or phase-sensitive detection (PSD). The dual-channel lock-in amplifier also provides both resistive and capacitive information of the nanowire in separate channels. Measurement results of test resistors and capacitors show a 2% resolution in the resistance range 10-40 kΩ and a 3% resolution in the capacitance range 0.5-1.8 nF. Moreover, a 28.7-32.1 kΩ impedance variation was measured through the lock-in amplifier for a single palladium nanowire that was exposed to a decreasing hydrogen concentration (10% H₂ in N₂ to air). The chip has been implemented with UMC 0.18 μm CMOS technology and occupies an area of 2 mm². The power consumption of the readout circuit is 2 mW from a 1.8 V supply.     

A low-power correlation-derivative CMOS VLSI circuit for bearing estimation

We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive algorithm decides which pair to use depending on the direction of the incoming signal, in such a way to obtain the best estimate. The IC contains two blocks with 104 stages each. Every stage has a delay unit, a block to reduce the clock speed, and a 10-bit UP/DN counter. The IC measures 2 mm by 2.4 mm, and dissipates 600 /spl mu/W at 3.3 V and 200 kHz. It is purely digital and uses a one-bit quantization of the input signals.     

一种低功耗高速空间光调制器驱动电路

本文描述了一种新型的多量子阱空间光调制器驱动电路的设计和测试。为了解决时钟同步问题并减少功耗,我们有别于前人,将所有电路模块集成在一块芯片上。因为传统的单斜坡数模转换器无法消除电容的失配,所以我们转而采用64个列共享8位电阻串数模转换器来提供输出电压,实现0.5V至3.8V的可编程电压调控。这些数模转换器被紧密放置于6464 驱动阵列的上方力求减小失配。每个转换器消耗80uA电流,在280ns内完成一次转换。为了更快的传输速率,系统采用2级缓存,工作时钟50MHz,真刷新率达到50K帧每秒,整片功耗302mW。芯片采用0.35um CMOS工艺,面积5.5 mm7 mm。     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

High-speed low-power cross-coupled active-pull-down ECL circuit

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 μm double poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.7× improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay, 2.1× improvement in the load driving capability, and 3.5× improvement in the dotting delay penalty compared with the conventional ECL circuit. The design considerations of the circuit are discussed     

A low-power,fast-settling reference circuit for high-speed high-resolution ADC

A low-power, fast-settling reference buffer used for high-speed high-resolution ADC is proposed. A replica buffer forms a closed loop to stabilise the operating point and a cascaded gm-boosting technique provides sufficient low output impedance, all of which ensure a high performance for the proposed buffer. The measured results show that the proportion of power consumption by the proposed buffer over ADC is only 2.7%, while settling to 12-bit accuracy within 0.13 ns.     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

一个低功耗低电压的二级运放压摆率增强电路

本文提出了一个新颖的二级运放压摆率增强电路。该电路采用AB类输入级,提高了电流效率。相对于运放,它完全开环工作,因此不会影响运放的稳定性。当运放处于压摆阶段时,电路检测运放输入差分电压,产生外部的动态电流并注入运放,从而使加快负载电容的充/放电过程。电路仿真结果显示：对于大的输入阶跃信号,该电路可以减少50%的建立时间;将电路运用于采样保持电路时,该电路提高了无杂散动态范围44.6dB,降低了总谐波失真43.9dB。本文提出的电路非常适用于低电压（1.2V或更低）工作,并且只消耗200μA的静态电流。     

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications

A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.     

电流自动可调低功耗LED驱动电路

LED光源作为新型绿色环保光源,具有寿命长,发光效率高,高亮度以及工作电压低等优点。基于LED驱动电路的过温保护以及降低功耗要求,本文设计了一种用正温敏电阻来自动调节LED驱动电流以及降低采样电阻功耗的LED驱动电路,与常用的LED驱动电路相比,其优点在于:在温度达到保护点时,驱动电流不是直接降为零,而是在不被人眼明显发觉光变的前提下,LED驱动电流随系统温度的增加而适当的降低,因此,更适应照明等领域。本文所选取的LED驱动电流为ILED=350mA,LED灯阵列由M×N矩阵形式组成。     

低功耗无线收发电路系统设计

目前,无线通信技术发展极其迅速,随之引起系统功耗不断上升。因此人们近几年来对无线通信网络中各方面的低功耗技术进行了深入的研究,使节能成为无线通信发展的一个重要方向。设计了低功耗无线收发电路系统,采用STM32L151系列超低功耗芯片和UTC4432系列无线通信模块作为核心电路系统,通过软件设计及调试实现整个低功耗收发电路系统功能。结果表明:采用合适的微控制器和无线通信模块对于控制无线收发电路系统的功耗有着极其重要的作用,再加上对软件编程的控制,能够使整个系统的功耗大幅度降低。     

A fast driver circuit for single-photon sensors

A fast active quenching and recharging circuit (AQRC) for single-photon avalanche diodes (SPAD) is presented in this paper. The proposed driver exhibits a lower than 10 ns overall quenching time allowing a tunable excess voltage from 5 to 12 V. The circuit was designed by using the dielectrically insulated BiCMOS technology supplied by ST Microelectronics. Many post-layout ELDO simulations have validated the high performance of the proposed topology, which is actually the fastest AQRC reported in the literature.     

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f/sub T/ and f/sub max/ of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.